A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS

Kuo, Ming Zhang; Hsieh, Henry; Dhong, S.H.; Yang, P.; Lin, Chen‐Ju; Tseng, Ryan; Huang, Kevin; Wang, Min Jer; Hwang, Wei

doi:10.1109/cicc.2014.6946030

Search citation statements

Order By: Relevance

Paper Sections

Select...

Introduction1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2014

Publication Types

Select...

Other1

Relationship

Self Cite1

Independent0

Authors

Journals

Cited by 1 publication

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the impressive low-power performance of these circuit families addresses only some of the required SOC design features. The We review four recent CMOS circuit advances, whose power is comparable to near-threshold circuits when operating close to its DVFS lower limit ("" 0.5 V) with a smaller chip area B. Embedded SRAM operations with internal signals derived from the system clock in lieu of self-timed circuitry [4] In a clock-derived design, activation of the sense amplifier (SA) starts with a delayed half-cycle clock as shown in Fig. 2.…”

Section: Introductionmentioning

confidence: 99%

Recent advances in ASIC-compatible circuit techniques for a SOC in newly emerging application areas: Invited paper

Dhong¹,

Hwang²

2014

2014 International SoC Design Conference (ISOCC)

Self Cite

View full text Add to dashboard Cite

We review advances in ASIC-compatible circuits for emerging SOC areas. These applications require ubiquitously low-power consumption during standby mode while providing a required performance in active mode. Sub-or near-threshold circuits may provide a low-power solution. However, they have yet to show how they fit into overall SOC optimization including area and performance. Selectively introducing custom-circuit techniques with ASIC tool compatibility have proven very attractive in reducing both the power and the area of a SOC by extending its Dynamic Voltage-Frequency Scaling (DVFS) range down to a VDD of 0.5 V.

show abstract

Section: Introductionmentioning

confidence: 99%