A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

Abstract

This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1][2][3][4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is -100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed, one must take into account the antagonist tradeoff between large band tuning range of the frequency synthesizer and phase noise performance. In transceivers using super-heterodyne architecture with double conversion, the frequency synthesizer signal f LO can be equal to 2f RF /3 and f RF /3. In this case, to cover the four channels of the IEEE 802.15.3c normalization, the frequency synthesizer has to deliver a first local oscillator (LO) signal between 19.44GHz and 21.6GHz and a second LO signal between 38.88GHz and 43.2GHz, respectively. This architecture offers a good trade off between the required large frequency tuning range (>15%) and low phase noise (<-95dBc/Hz).The PLL architecture is depicted in Fig. 13.5.1. It is composed of a Push-Push Quadrature-Voltage-Controlled-Oscillator (QVCO) that delivers two 0°/90° LO signals around 20GHz and a harmonic signal around 40GHz. The QVCO is followed by a frequency divider chain with a division ratio varying from 640 to 1240. Next, the Phase/Frequency Detector (PFD) compares the VCO's divided signal to an external 36MHz reference signal which is divided by two. Finally, a Charge Pump (CP) followed by a 3 rd order Loop Filter (LF) controls the QVCO's oscillation frequency. Figure 13.5.2 shows the schematic of the QVCO. It is based on two cross coupled CMOS VCOs (MI_1 … MI_4 and MQ_1 … MQ_4). In order to generate the 0°/90° oscillation signals each basic VCO cell is coupled by two NMOS transistors (MI_5, MI_6 and MQ_5, MQ_6). The global QVCO oscillates around 20GHz. Each cell's resonator includes a single octagonal integrated inductance and a bank of varactors. The bank uses many varactors for oscillation frequency control. One of the varactors is connected to the loop filter (LF) voltage control (analog varactor) and the others are switched ON and OFF with the help of a 4 bits digital control (digital varactors). This technique helps to split the required oscillation band into sub-bands and to reduce the oscillator's gain for better PLL global stability. The oscillation sub-bands overlap between them thanks to a judicious choice of each of the varactors size. The required 40GHz signal is collected at the current source of the coupling transistors with the help of two shortended quarter wave transmission line...

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

“…This range covers operation over 22. [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. 4 GHz, with margin, meeting requirements for a 60-GHz superheterodyne radio [2].…”

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“…이중에서 직접 변환 방식 [1]～ [3] 은 DC 오프셋, I/Q 부정합, LO 피드스루(feed-through)와 같은 단점들이 존재한다. 따라서 그러한 문제점들을 회피함과 동시에, 상대적으로 낮은 출력 주파수와 작은 K VCO 로 설계할 수 있는 슬라이딩-IF 구조 [4]～ [6] 가 더욱 선호된다. [5], [8] .…”

Analysis and Design of a 14.1-mW 50/100-GHz Transformer-Based PLL With Embedded Phase Shifter in 65-nm CMOS

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