A 18 μA-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode

Abstract

A 1.8V 200MHz low-subthreshold-leakage-current microprocessor is fabricated in a 0.2pm CMOS technology. It uses a switched substrate-impedance scheme to bias substrates while maintaining 200MHz operating speed. It also offers a battery backup capability in a self substrate-biased data retention mode, in which it consumes only 17.8pA operating off a 1.OV supply.To achieve a low retention current, we introduce two standby modes in the microprocessor described in ISSCC98 (i.e., standby mode and data retention mode) [l]. In both modes, body effect reduces subthreshold leakage current. Although a number of techniques using body effect are reported, there have not been any successful reports on their application to million-transistor microprocessors above lOOMHz [ Z ] . This is mainly because highspeed switching of MOS transistors induces local power-supply noise and local substrate noise. These noises make it difficult to bias the substrates of all MOS transistors uniformly. The switched substrate-impedance scheme controls substrate bias. This scheme switches substrate impedance according to the operation modes. To provide battery backup capability, the self substrate-biased data-retention mode exploits a substrate-bias-assisted draininduced-barrier-lowering (DIBL) effect. Figure 16.4.1 illustrates the switched substrate-impedance scheme.A standby controller and a VBC macro control the voltage of the substrates (denoted a s vhp for a PMOS substrate and vbn for a n nMOS substrate) in the 1.8V logic circuit. In standby mode, these are driven with a high-voltage high-output-impedance driver in the VBC macro. In contrast, in active mode, the substrates are driven with about 10,000 switch cells distributed over a n entire chip. One switch cell consists of two 3.3V high-Vth MOS transistors; one transistor with a gate signal connected to cbp connects vbp and vdd, while the other transistor with a gate signal connected to cbn connects vbn and vss. These transistors reduce the substrate impedance. They keep the substrate biases of MOS transistors equal to their local power supplies.The VBC macro consists of four circuits, VBCP, VBCN, VBCI and VBCG, and is fed by two supply voltages, vdd (normally 1.8V) and vwell (3.3V). Four signals (vbp, cbp, vbn, and cbn) are generated by VBCP and VBCN. To drive many switch cells without causing significant simultaneous switching noise, the VBC macro uses a feedback loop formed by cbp, cbn and by their feedback signals, cbpr and cbnr. VBCI senses these feedback signals and sends them to VBCP and VBCN. Moreover, VBCG generates vsub voltage according to the following equation: vsub = vddvwell, which is a negative voltage used as the third voltage source in the VBC macro (Figure 16.4.1).Figure 16.4.2a shows the metal interconnections of vbp, vbn, cbp, cbn and power lines. In conventional CMOS, the substrates (vbp and vbn) are connected to the power lines (vdd and vss) locally. In contrast, they should he interconnected separately for biasing the substrate. The microprocessor has five levels of...

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