2021
DOI: 10.1109/tbcas.2021.3062377
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A 19 μW, 50 kS/s, 0.008-400 V/s Cyclic Voltammetry Readout Interface With a Current Feedback Loop and On-Chip Pattern Generation

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Cited by 14 publications
(1 citation statement)
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“…Although it is possible to integrate a few 150 pF capacitors using CMOS technology, it is challenging to integrate 100s of amplifiers. Current division or current subtraction can be used to decrease the required capacitance [21][22][23]; however, they come with a cost of power, area, or noise performance. An analog front-end with analog background subtraction was able to achieve high bandwidth (5 kHz) and low noise level (26.5 pARMS), however, the analog front-end size was relatively larger (0.256 mm 2 ) compared to other works that can achieve similar dynamic range [23].…”
Section: Introductionmentioning
confidence: 99%
“…Although it is possible to integrate a few 150 pF capacitors using CMOS technology, it is challenging to integrate 100s of amplifiers. Current division or current subtraction can be used to decrease the required capacitance [21][22][23]; however, they come with a cost of power, area, or noise performance. An analog front-end with analog background subtraction was able to achieve high bandwidth (5 kHz) and low noise level (26.5 pARMS), however, the analog front-end size was relatively larger (0.256 mm 2 ) compared to other works that can achieve similar dynamic range [23].…”
Section: Introductionmentioning
confidence: 99%