A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver

Busson, P.; Chawla, Nitin; Bach, J.; Tual, Stephane Le; Singh, Harpal; Gupta, Vishal; Urard, Pascal

doi:10.1109/isscc.2009.4977406

Cited by 2 publications

(2 citation statements)

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“…Within this section we present some concrete results related to a circuit designed in a 65 nm CMOSLPGP mix technology. This 1GHz Digital Channel Multiplexer for Satellite Outdoor Unit has a silicon area of 12.75 mm² and a digital total power of 950mW for standard parts at 1V supply voltage as described in reference [7].…”

Section: -E-experimental Resultsmentioning

confidence: 99%

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Moubdi

Maurine

Wilson

et al. 2010

Lecture Notes in Computer Science

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This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. Concrete results are introduced in this paper to demonstrate the added value of such a methodology. More precisely, it is shown that its application leads to an overall energy reduction ranging from 10% to 20% on fast chips.

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Section: -E-experimental Resultsmentioning

confidence: 99%

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Moubdi

Maurine

Wilson

et al. 2010

Lecture Notes in Computer Science

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“…An existing solution called analog single-wire multiswitch (ASWM) channel stacking uses an analog frequency translation switch located near the antenna LNB to select and output signals from multiple LNB's to a fixed frequency slot for each set-top box on a single cable [1]. Although the ASWM solution solves the problem of multiple cables, it does not provide enough flexibility and capability to increase the number of inputs, and it requires multiple external components like SAW filters which in turn would significantly increase cost [2]. This paper introduces an integrated digital single-wire multiswitch (DSWM) channel-stacking IC implemented in 45nm CMOS, which uses digital signal processing after wideband 9b 1.82GS/s ADC's to select and reorder transponder channels.…”

mentioning

confidence: 99%

A digital single-wire multiswitch (DSWM) channel-stacking IC in 45nm CMOS for satellite outdoor units

Gao

Huff²,

Hess

et al. 2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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The evolution of direct-to-home transmit/receive systems requires a solution to aggregate, switch and route signals from multiple satellites to multiple set-top boxes efficiently. Prior solutions required separate coax cables to carry signals from each low-noise block (LNB) to set-top boxes in the home, resulting in high installation cost. An existing solution called analog single-wire multiswitch (ASWM) channel stacking uses an analog frequency translation switch located near the antenna LNB to select and output signals from multiple LNB's to a fixed frequency slot for each set-top box on a single cable [1]. Although the ASWM solution solves the problem of multiple cables, it does not provide enough flexibility and capability to increase the number of inputs, and it requires multiple external components like SAW filters which in turn would significantly increase cost [2]. This paper introduces an integrated digital single-wire multiswitch (DSWM) channel-stacking IC implemented in 45nm CMOS, which uses digital signal processing after wideband 9b 1.82GS/s ADC's to select and reorder transponder channels. The selected and reordered channels are digitally upconverted and are stacked into L-band through a 9b 5.46GS/s DAC. It removes the need of in-band SAW filters, offers a full flexibility of channel selection, and supports many more satellites through a single L-band cable to set-top boxes at much lower cost and lower power consumption. Figure 13.8.1 shows a simplified block diagram of the DSWM chip with its associated interface components. There are 14 separate RF inputs each accepting transponder channels in B-band from 250MHz to 760MHz. These input fullspectrum bands are individually level adjusted by the front-end RF stepped variable gain amplifiers and sampled by the following ADC's, and subsequently sent to the DSP unit for channelization, selection, and frequency re-ordering. The DAC takes re-ordered and level-adjusted channels from the DSP unit and outputs the transponder channels in L-band from 950MHz to 2150MHz. All required clock signals are generated by the on-chip PLL frequency synthesizer and frequency dividers. The FSK transceiver along with the rest of the digital system control unit communicates with set-top boxes and assigns them channels for distribution of the transponder signals. There are temperature, process corner and IR drop sensors for various purposes such as chip test and characterization, circuit calibration and optimization, and over-heating prevention. All internal circuit blocks are testable via scan tests for digital blocks, test mux and demux for PLL and data converters, control and test interfaces, and inter-stage input and output pins.The signal chain impairment budget requires a variable gain amplifier having 30dB gain dynamic range with step size less than 0.75dB, an OIP3 of 8dBVp, and NF smaller than 15dB at the maximum gain. A digitally controlled stepped variable gain RF amplifier is implemented to fulfill the requirements. It has a frontend coarse step variable-gain attenua...

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A 1GHz digital channel multiplexer for satellite OutDoor Unit based on a 65nm CMOS transceiver

Cited by 2 publications

References 4 publications

Product On-Chip Process Compensation for Low Power and Yield Enhancement

Product On-Chip Process Compensation for Low Power and Yield Enhancement

A digital single-wire multiswitch (DSWM) channel-stacking IC in 45nm CMOS for satellite outdoor units

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