A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics

Han, Jinho; Kwon, Young–Se; Cho, Yong Cheol Peter; Yoo, Hoi‐Jun

doi:10.1109/asscc.2017.8240279

Cited by 7 publications

(8 citation statements)

References 3 publications

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“…The AB9 SoC includes four Aldebaran cores [1] that run the 32-bit SPARC instruction set architecture (ISA) at 1 GHz. Two of the four cores in the quad-core setup can be configured to run in the lock-step mode for safety critical applications [2]. The AB9 SoC was designed for both embedded and server environments.…”

Section: Architecturementioning

confidence: 99%

“…The SoC is equipped with two LPDDR4 memory controllers, each with a bandwidth of up to 170 Gbps as well as a PCIe interface. The AB9 SoC is implemented using TSMC 28-nm process technology with a chip area of 17 × 23 mm 2 . Figure 1 shows a block diagram of the major components in AB9.…”

Section: Architecturementioning

confidence: 99%

“…With a custom design targeting NN acceleration, the STC accelerator and its development environment are optimized to enhance performance and efficiency while maintaining programmability to accommodate various NN types. The AB9 SoC uses TSMC 28-nm process technology with a chip area of 17 × 23 mm 2 .…”

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confidence: 99%

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AB9: A neural processor for inference acceleration

et al. 2020

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We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on‐chip memory. Complementing the hardware is an intuitive and user‐friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40‐TFLOP STC that includes 32k arithmetic units and over 36 MB of on‐chip SRAM, our baseline implementation of AB9 consists of a 1‐GHz quad‐core setup with other various industry‐standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general‐purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28‐nm process with a chip size of 17 × 23 mm2. Delivery is expected later this year.

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Section: Architecturementioning

confidence: 99%

Section: Architecturementioning

confidence: 99%

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AB9: A neural processor for inference acceleration

et al. 2020

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“…The processor works in tandem with the 128 × 128 processing cores. [26] The proposed fault-tolerant processor contains two key features: (a) DLS with separate clock and power sources to reduce dependent failures or achieve high performance and (b) a cache with the self-recovering function to reduce the instances of transient faults and a reconfigurable function to reduce the instances of permanent faults.…”

Section: General-purpose Processormentioning

confidence: 99%

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

2020

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The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function‐safe architecture is proposed for a fault‐tolerance system such as an electronics system for autonomous cars. The general‐purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self‐recovering cache and dynamic lockstep function. The function‐safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28‐nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function‐safe design can have ISO26262 ASIL‐D with the single‐point fault‐tolerance rate of 99.64%.

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“…As part of the efforts for developing solutions to address the demands of Autonomous Driving, industry and academia are investing in research on several related areas. Several works are exploring aspects of fault-tolerance in hardware architectures [1], [2], software design [3], operational systems [4], among others. [5] provides a broader look on specific reliability challenges for autonomous systems, for both automotive and robotics.…”

Section: Introductionmentioning

confidence: 99%

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

Silva

Bagbaba

Ruospo

et al. 2020

2020 IEEE 38th VLSI Test Symposium (VTS)

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The current demands for autonomous driving generated momentum for an increase in research in the different technologies required for these applications. Nonetheless, the limited access to representative designs and industrial methodologies poses a challenge to the research community. Considering this scenario, there is a high demand for an open-source solution that could support development of research targeting automotive applications. This paper presents the current status of AutoSoC, an automotive SoC benchmark suite that includes hardware and software elements and is entirely open-source. The objective is to provide researchers with an industrial-grade automotive SoC that includes all essential components, is fully customizable, and enables analysis of functional safety solutions and automotive SoC configurations. This paper describes the available configurations of the benchmark including an initial assessment for ASIL B to D configurations.

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A 1GHz fault tolerant processor with dynamic lockstep and self-recovering cache for ADAS SoC complying with ISO26262 in automotive electronics

Cited by 7 publications

References 3 publications

AB9: A neural processor for inference acceleration

AB9: A neural processor for inference acceleration

40‐TFLOPS artificial intelligence processor with function‐safe programmable many‐cores for ISO26262 ASIL‐D

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks

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