A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

Lee, Seungjae; Kim, Chulbum; Kim, Minsu; Joe, Sung-Min; Jang, Joonsuc; Kim, Seungbum; Lee, Kangbin; Kim, Jisu; Park, Jiyoon; Lee, Han-Jun; Kim, Minseok; Lee, Seonyong; Lee, SeonGeon; Bang, Jinbae; Shin, Dong‐Jin; Jang, Hwajun; Lee, Deokwoo; Kim, Nahyun; Jo, Jonghoo; Park, Jonghoon; Park, Sohyun; Rho, Youngsik; Park, Yongha; Kim, Hojoon; Lee, Cheon An; Yu, Chungho; Min, Young-Sun; Kim, Moosung; Kim, Kyungmin; Moon, Seunghyun; Kim, Hyun‐Jin; Choi, Yong‐Sang; Ryu, YoungHwan; Choi, Jin-Won; Min-Yeong, Lee; Kim, Jungkwan; Choo, Gyo Soo; Lim, Jeong-Don; Byeon, Dae–Seok; Song, Ki–Whan; Park, Kitae; Kyung, Kye-Hyun

doi:10.1109/isscc.2018.8310323

Cited by 81 publications

(30 citation statements)

References 2 publications

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“…Here, N is the electron numbers in nitride layer of NAND flash memory after ISPP program for a page memory cells, P t is the average electron emission probability between time 0 (program finished) and time t (data retention operation), n is the emitted electrons numbers from nitride layer for a page memory cells, and P(n) is the probability of emitted n electrons for a page memory cells. Thus, its mean n (can be obtained from measurements) and the variance σ 2 EEES can be written as eq. 5and 6:…”

Section: Models a Essential Electron Emission Statisticsmentioning

confidence: 99%

“…Then, we can obtain the relationship between the variance of retention noise σ 2 noise and the mean n of emitted electron numbers due to effect of essential electron emission statistics (EEES) can be expressed as eq. 7:…”

Section: Models a Essential Electron Emission Statisticsmentioning

confidence: 99%

“…Finally, the relationship between the variance of retention noise σ 2 noise and the mean n of emitted electron numbers can be written as eq. 21:…”

Section: Device Parameters Fluctuationmentioning

confidence: 99%

“…At the same time, in order to further increase the storage capacity of NAND flash memory, multi-level program cell (MLC) and triple-level program cell (TLC) technologies are introduced. 3-D quad-level program cell (QLC) NAND flash memory [2] is a promising candidate for lower power operation, and higher density nonvolatile memory. However, data retention errors are the dominant sources of NAND flash memory fail bit counts (FBCs), which is one of the most important challenges to realize multi-bit-percell (MB) technologies due to the extremely narrow read V th windows.…”

Section: Introductionmentioning

confidence: 99%

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Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Wang

Lun³

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, the retention noise [electron emission statistics (EES)] after program operation of 3-D triple-level program cell (TLC) NAND flash memory is investigated. Three main noise sources, consisting of essential EES (EEES), electron numbers fluctuation, and device parameters fluctuation to broaden the retention V th distributions are comprehensively considered, and the corresponding analytic models are developed. The impact of device parameters fluctuation is relatively larger than EEES and electron numbers fluctuation for our measured 3-D TLC NAND flash memory devices. Using the proposed models, the calculated V th distributions after different data retention times have good agreements with the measurements, which validate our proposed models. This paper provides a method to predict the V th distributions accurately and efficiently, and can help in improving reliability of 3-D TLC and quad-level program cell NAND flash memory. INDEX TERMS Retention V th distribution, retention noise, 3-D TLC NAND flash memory, reliability.

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Section: Models a Essential Electron Emission Statisticsmentioning

confidence: 99%

Section: Models a Essential Electron Emission Statisticsmentioning

confidence: 99%

“…Finally, the relationship between the variance of retention noise σ 2 noise and the mean n of emitted electron numbers can be written as eq. 21:…”

Section: Device Parameters Fluctuationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Wang

Lun³

et al. 2019

IEEE J. Electron Devices Soc.

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“…In particular, the transition from 2-D NAND flash memory to 3-D NAND flash memory has been raising many new challenges [15]. 3-D quad-level cell (QLC) NAND flash memory technology is a promising candidate for lower cost per bit and higher-density nonvolatile memory [16,17]. However, for 3-D TLC and QLC NAND flash memories, a narrow program Vth distribution interval is very important.…”

Section: Introductionmentioning

confidence: 99%

Modeling of program Vth distribution for 3-D TLC NAND flash memory

Wang

Lun

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a simulation method to model the program Vth distribution of 3-D vertical channel TLC/QLC charge-trapping NAND flash memory. The program Vth distribution can be calculated by considering ISPP noise, WL-WL interference, and the RTN effect of tunneling oxide and poly Si, which are the major physical factors affecting the width of program Vth distribution. Then, the program Vth distribution shapes with different ISPP incremental voltage steps are compared, and the results are found to be consistent with the experimental results. Code and layer-dependent coupling coefficients of WL-WL interference in 3-D vertical channel NAND flash memory are considered. The effect of RTN on the program Vth distribution is comprehensively studied. The program Vth distribution of a WL is calibrated with the measurement, and a good agreement is obtained, validating the array program Vth distribution simulation method. The simulation method can help in improving the reliability of 3-D TLC NAND flash memory and provides guidance for the design and optimization of 3-D QLC NAND flash memory technology.

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Review of Semiconductor Flash Memory Devices for Material and Process Issues

et al. 2022

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Vertically integrated NAND (V‐NAND) flash memory is the main data storage in modern handheld electronic devices, widening its share even in the data centers where installation and operation costs are critical. While the conventional scaling rule has been applied down to the design rule of ≈15 nm (year 2013), the current method of increasing device density is stacking up layers. Currently, 176‐layer‐stacked V‐NAND flash memory is available on the market. Nonetheless, increasing the layers invokes several challenges, such as film stress management and deep contact hole etching. Also, there should be an upper bound for the attainable stacking layers (400–500) due to the total allowable chip thickness, which will be reached within 6–7 years. This review summarizes the current status and critical challenges of charge‐trap‐based flash memory devices, with a focus on the material (floating‐gate vs charge‐trap‐layer), array‐level circuit architecture (NOR vs NAND), physical integration structure (2D vs 3D), and cell‐level programming technique (single vs multiple levels). Current efforts to improve fabrication processes and device performances using new materials are also introduced. The review suggests directions for future storage devices based on the ionic mechanism, which may overcome the inherent problems of flash memory devices.

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A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput

Cited by 81 publications

References 2 publications

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Investigation of Retention Noise for 3-D TLC NAND Flash Memory

Modeling of program Vth distribution for 3-D TLC NAND flash memory

Review of Semiconductor Flash Memory Devices for Material and Process Issues

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