A 1V 22µW 32-channel implantable EEG recording IC

Abstract

Epilepsy is one of the most common neurological disorders and affects more than 50 million individuals worldwide. Neurosurgery is an option for patients and intracranial EEG monitoring needs to be performed before surgery, which requires a multi-channel implantable EEG device. This paper presents a 1V 32channel reconfigurable sensor interface IC for intracranial EEG recording. The power consumption of the overall system including amplification, filtering, and 10b ADC is 22µW, which makes it suitable for other implantable applications such as deep-brain stimulation.According to [1], the input-referred noise for an implantable EEG device should be less than 1.5µV rms . A chopper-stabilized instrumentation amplifier [1-2] is not used in our design. The system architecture of the chip is shown in Fig. 6.7.1. It consists of 32 analog front-end blocks, a 32-to-1 multiplexer, a 10b SAR-ADC and a reference generator. Each of the analog blocks is implemented using 3 cascaded stages. The first stage is a low-noise front-end amplifier with high-pass function. The second stage acts as a tunable low-pass filter providing adjustable gain. The last stage uses a wide bandwidth unity-gain buffer with high slew rate to achieve an acceptable tracking error. The architecture differs from existing biomedical sensor interface chips where single or twin-amplifier structures are usually used to conserve power [3][4]. Utilizing fewer amplifiers does not necessarily lead to optimum designs in terms of power and chip area, especially for multi-channel applications. In conventional biomedical systems, the low-pass function is usually integrated with the front-end amplifier [3][4][5], and its -3dB frequency is determined by f -3dB =g m /(C C ·A V ), where g m is the transconductance of the input pair, C C is the load capacitance or Miller compensation capacitance and A V is the midband gain. Since the noise figure of the front-end amplifier is inversely proportional to g m , a low noise floor requires g m to be as large as possible. As a result, a large value of C C is necessary if f -3dB is in the low frequency range. EEG recording requires less than 150Hz bandwidth [1], which leads to a large value of C C in the 10's of pF. These capacitors consume large silicon area for multi-channel designs. In our system architecture, we avoid using a large C C by separating the role of noise suppression and low-pass functionality. The first stage is dedicated to noise suppression using g m as large as possible but without C C . The low-pass filter is realized in the second stage, whose noise is insignificant to the noise figure of the overall system. Thereby a small g m is adequate and C C is reduced by 85% compared to the design in [3][4]. Another advantage of the system architecture is its flexibility in balancing system performance and power efficiency. For example, almost all the current of the front-end amplifier is devoted to achieve low noise, without worrying about other trade-offs, such as area, gain or bandwidth. For the unity-gain buffer, a ...

Active Electrodes for Wearable EEG Acquisition: Review and Electronics Design Methodology

“…To avoid the need for an external component, an on-chip pseudo-resistor [27] was implemented (see Section III.C), at the cost of nonlinearity and inaccuracy of the resistance. The power of a capacitively coupled inverting amplifier can be further reduced by optimizing its core amplifier [31]- [33]. Apart from the general guidelines of low-power amplifiers (see Section V.A), a state-of-the-art bio-amplifier [34] achieves low noise of 0.34µVrms with only 1.17µW power, corresponding to a noise-efficiency-factor (NEF) of 1.74.…”

“…However, novel circuit techniques can achieve the same target with low power. Current reuse [33], e.g. by using an inverter-based input transistors consisting of series-connected NMOS and PMOS (Fig.…”

A Single-Ended ADC with Split Dual-Capacitive-Array for Multi-Channel Systems

“…In the design of ADCs for these applications, successive-approximation register (SAR) architectures with segmented capacitive array would be the most preferred solution owing to inherent low-power consumption and small area compared with other type ADCs [1][2][3][4][5].…”

“…One of the previous segmented SAR architectures [1] reduces the switching energy in capacitive array, however higher sampling operations and larger area are required for analog front-ends (AFEs) as the number of channels increases due to the use of a single sample-andhold (S/H) circuit. The architecture using analog multiplexing scheme [2] adopts 2-branch pipelined S/H to reduce the sampling frequency of the AFEs, which needs additional large S/H capacitor.…”

“…Because the required number of comparators is proportionally increased as the number of channels increases, offset mismatches among multiple comparators is problematic for better linearity in [3]. In addition, the kickback noise of segmented SAR architectures [1][2][3] causes linearity performance degradation since the load capacitances at two comparator inputs are different. Another segmented SAR architecture is the split capacitor array scheme with attenuation capacitors, which can be applied to both a single-ended and a differential-input SAR ADC [4].…”