A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS

Abstract

We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibreoptic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140.The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25x50m 2 . Keywords-Multi-modulus divider, frequency divider, prescaler, true single-phase clocked (TSPC) logicI.

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

“…Recently, inductorless divider designs employed the CML family or True-Single-Phase-Clock (TSPC) logic family to increase the speed. Several design examples can be found in the literature [15]- [19].…”