A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications

Lee, Seongju; Kim, Kyuyoung; Oh, Sanghoon; Park, Joonhong; Hong, Gi-Moon; Ka, Dongyoon; Hwang, Kyu-Dong; Park, Jeongje; Kang, Kyeong-Pil; Kim, Jungyeon; Jeon, Junyeol; Kim, Nahsung; Kwon, Yongkee; Vladimir, Kornijcuk; Shin, Woojae; Won, Jongsoon; Lee, Min-Kyu; Joo, Hyunha; Choi, Haerang; Lee, Jae‐Wook; Ko, Donguc; Jun, Younggun; Cho, Keewon; Kim, Ilwoong; Song, Choungki; Jeong, Chunseok; Kwon, Daehan; Jang, Jieun; Park, Il; Chun, Junhyun; Cho, Joohwan

doi:10.1109/isscc42614.2022.9731711

Cited by 58 publications

(38 citation statements)

References 6 publications

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“…We anticipate consumer use-cases to continue diversifying, making a ordable-yet-exible DRAM increasingly important. Ambitious initiatives such as DRAM-system codesign [87,117,118,241,242] and emerging, non-traditional DRAM architectures [119,198,241,326,327,[357][358][359][360][361][362] will naturally engender transparency by tightening the relationship between DRAM manufacturers and system designers. Regardless of the underlying motivation, we believe that increased transparency of DRAM reliability characteristics will remain crucial to allowing system designers to make the best use of commodity DRAM chips by enabling them to customize DRAM chips for system-level goals.…”

Section: Alternative Futuresmentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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Mass-produced commodity DRAM is the preferred choice of main memory for a broad range of computing systems due to its favorable cost-per-bit. However, today's systems have diverse system-speci c needs (e.g., performance, energy, reliability) that are di cult to address using one-size-ts-all generalpurpose DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by exploiting slack in access timings to improve performance, or implementing system-level RowHammer mitigations), we observe that designers today lack the necessary insight into commodity DRAM chips' reliability characteristics to implement these techniques in practice. In this work, we make a case for DRAM manufacturers to provide increased transparency into simple device characteristics (e.g., internal row address mapping, cell array organization) that a ect consumer-visible reliability. Doing so has negligible impact on manufacturers given that these characteristics can be reverse-engineered using known techniques; however, it has signi cant bene t for system designers, who can then make informed decisions to be er adapt commodity DRAM to meet modern systems' needs while preserving its cost advantages.To support our argument, we study four ways that system designers can adapt commodity DRAM chips to system-speci c design goals: (1) improving DRAM reliability; (2) reducing DRAM refresh overheads; (3) reducing DRAM access latency; and (4) defending against RowHammer a acks. We observe that adopting solutions for any of the four goals requires system designers to make assumptions about a DRAM chip's reliability characteristics. ese assumptions discourage system designers from using such solutions in practice due to the di culty of both making and relying upon the assumption.We identify DRAM standards as the root of the problem: current standards rigidly enforce a xed operating point with no speci cations for how a system designer might explore alternative operating points. To overcome this problem, we introduce a two-step approach that reevaluates DRAM standards with a focus on transparency of reliability characteristics so that system designers are encouraged to make the most of commodity DRAM technology for both current and future DRAM chips.

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Section: Alternative Futuresmentioning

confidence: 99%

A Case for Transparent Reliability in DRAM Systems

Patel¹,

Shahroodi²,

Manglik³

et al. 2022

Preprint

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“…Memory manufacturers recently introduced real PIM systems that target different application domains (e.g., neural networks[95][96][97][98]108], generalpurpose computing[109][110][111]) and memory technologies (e.g., 3D-stacked DRAM[97,98,108], 2D DRAM[95,96,110,111], non-volatile memories[112]). …”

mentioning

confidence: 99%

Enabling High-Performance and Energy-Efficient Hybrid Transactional/Analytical Databases with Hardware/Software Cooperation

Boroumand¹,

Ghose²,

F.³

et al. 2022

Preprint

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A growth in data volume, combined with increasing demand for real-time analysis (using the most recent data), has resulted in the emergence of database systems that concurrently support transactions and data analytics. These hybrid transactional and analytical processing (HTAP) database systems can support real-time data analysis without the high costs of synchronizing across separate single-purpose databases. Unfortunately, for many applications that perform a high rate of data updates, state-of-the-art HTAP systems incur significant losses in transactional (up to 74.6%) and/or analytical (up to 49.8%) throughput compared to performing only transactional or only analytical queries in isolation, due to (1) data movement between the CPU and memory, (2) data update propagation from transactional to analytical workloads, and (3) the cost to maintain a consistent view of data across the system.We propose Polynesia, a hardware-software co-designed system for in-memory HTAP databases that avoids the large throughput losses of traditional HTAP systems. Polynesia (1) divides the HTAP system into transactional and analytical processing islands, (2) implements new custom hardware that unlocks software optimizations to reduce the costs of update propagation and consistency, and (3) exploits processing-in-memory for the analytical islands to alleviate data movement overheads. Our evaluation shows that Polynesia outperforms three stateof-the-art HTAP systems, with average transactional/analytical throughput improvements of 1.7×/3.7×, and reduces energy consumption by 48% over the prior lowest-energy HTAP system.

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“…PIM moves computation close to application data by equipping memory chips with processing capabilities [1,14,15]. To provide large aggregate memory bandwidth for the in-memory processors, several manufacturers have already started to commercialize nearbank PIM designs [1,9,10,19,20]. Near-bank PIM designs tightly couple a PIM core with each DRAM bank, exploiting bank-level parallelism to expose high on-chip memory bandwidth of standard DRAM to processors.…”

mentioning

confidence: 99%

“…Near-bank PIM designs tightly couple a PIM core with each DRAM bank, exploiting bank-level parallelism to expose high on-chip memory bandwidth of standard DRAM to processors. Three real near-bank PIM architectures are Samsung's FIMDRAM [19], SK hynix's GDDR6-AiM [20] and the UPMEM PIM system [1,9,10].…”

mentioning

confidence: 99%

“…Most real near-bank PIM architectures [1,9,10,19,20] support several PIM-enabled memory chips connected to a host CPU via memory channels. Each memory chip comprises multiple lowpower PIM cores with relatively low computation capability [9,10], and each of them is located close to a DRAM bank [9,10,19,20]. Each PIM core can access data located on its local DRAM bank, and typically there is no direct communication channel among PIM cores.…”

mentioning

confidence: 99%

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