A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider

Abstract

Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoM J ) that quantifies the power-jitter tradeoff is at least 25 dB worse than their LC-oscillator-based FNPLL counterparts. This paper seeks to close this performance gap by extending PLL bandwidth (BW) using quantization noise cancellation techniques and by employing a dual-path digital loop filter to suppress the detrimental impact of DAC quantization noise. Fabricated in 65 nm CMOS process, the proposed FNPLL operates over a wide frequency range of 2.0-5.5 GHz using a modified extended range multi-modulus divider with seamless switching. The proposed digital FNPLL achieves 1.9 ps rms integrated jitter while consuming only 4 mW at 5 GHz output. The measured in-band phase noise is better than −96 dBc/Hz at 1 MHz offset. The proposed FNPLL achieves wide BW up to 6 MHz using a 50 MHz reference and its FoM J is −228.5 dB, which is the best among all reported ring-based FNPLLs.

A modified pulse swallow frequency divider for fractional-N PLL

“…The divide-by-4/5 dual-modulus prescaler consists of three DFF, namely DFF0, DFF1, and DFF2. The implemention of these DFFs use true-single phase clock (TSPC) structure, which reduce the power consumption [4,5,6,29,30]. The DFFs outputs are defined as qb 0 , q 1 , and q 2 , and the divider state is defined as "qb 0 q 1 q 2 ", where the next state is calculated using: qb 0 + = qb 0 ', q 1 + = qb 0 , and q 2 + = qb 2 *q 1 + q 2 *q 1 '.…”

A compact and low-power wireless receiver for implanted medical backscatter

“…The digital loop is similar to the proportional-integral loop filter in [16] and drives the VCO via two ports-the fine bits to turn on/off the switchable capacitors at VCO nodes and the other coarse bits to a voltage sigma-delta DAC that effectively regulates the VCO supply and hence adjusting the VCO frequency [17]. The circuit is also much simpler than the ADPLL is [23], [26] and [27].…”

A wideband low-jitter PLL with an optimized Ring-VCO

“…An attractive method uses hybrid loops to achieve low jitter PLLs [18,19,20], as well as results in rather complicated circuits. More and more digital PLLs [21,22,23,24,25,26] are designed due to the advantages in terms of power, area, and programmability, whereas the improvement is needed in the jitter performance of digital PLLs. The Ring-VCO is the most important component of the PLL, in which the low phase noise and wideband characteristics directly determine the jitter and frequency range of PLLs.…”