A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

Tokairin, Takashi; Okada, Michiyo; Kitsunezuka, Masaki; Maeda, Tadashi; Fukaishi, M.

doi:10.1109/jssc.2010.2076591

Cited by 78 publications

(45 citation statements)

References 10 publications

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“…1 (a); and feedback-divider-less counter-based topology [3], [4], [5], [10], [11], [12], [13], [14], [15], [16], as shown in Fig. 1 (b).…”

Section: Adpll Categoriesmentioning

confidence: 99%

“…ADPLL implementations also include Refs. [6], [7], [8], [10], [11], [12], [13], [14] and [25]. It should be noted that there have been reported other all-digital PLL implementations, such as Refs.…”

Section: Figmentioning

confidence: 99%

“…( 1 ) The integer part of the phase error (φ EI [k]) keeps zero in the normal operation so it can be turned off after the PLL frequency acquisition to reduce the power consumption; ( 2 ) It significantly reduces the required operating range of the TDC, and makes it feasible to employ various highresolution TDCs to achieve better noise performance; ( 3 ) Both DTC and TDC operate at reference rate (the minimum possible rate for the phase error detection) without the need for additional power management circuitry [14], [19], thus resulting in significant power savings; ( 4 ) The fractional part of the phase error, φ EF [k], may be measured (and normalized based on TDC resolution) directly from the narrow TDC; ( 5 ) Because the signal FREF D is aligned with CKV, the complexity and the power consumption of CKR generation circuit and CKV gating clock circuit is significantly reduced.…”

Section: Principle Of Phase Predictionmentioning

confidence: 99%

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All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.

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“…1 (a); and feedback-divider-less counter-based topology [3], [4], [5], [10], [11], [12], [13], [14], [15], [16], as shown in Fig. 1 (b).…”

Section: Adpll Categoriesmentioning

confidence: 99%

Section: Figmentioning

confidence: 99%

Section: Principle Of Phase Predictionmentioning

confidence: 99%

See 1 more Smart Citation

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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“…While integrating a loop filter has been a challenging task in the conventional PLL design, removing the analog loop filter is considered an alternative solution in the recent PLL works [1][2][3][4][5][6][7][8][9][10][11][12][13]. However, the all-digital PLL (ADPLL) requires a high-resolution complex time-to-digital converter (TDC) which requires advanced CMOS technology.…”

Section: Design Issues In All-digital Pllmentioning

confidence: 99%

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Rhee

Wang

2011

Journal of Electrical and Computer Engineering

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This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

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“…In addition to the pioneering effort by Texas Instruments, there have been a large number of other commercial realizations of all-digital PLL's, for example [23]- [25]. An extensive recent survey of transceiver solutions and related patents filed by several companies may be found in [25].…”

Section: Introductionmentioning

confidence: 99%

Built-In Measurements in Low-Cost Digital-RF Transceivers

Eliezer

Staszewski

2011

IEICE Trans. Electron.

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SUMMARYDigital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRP TM ) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and builtin self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined. key words: system-on-chip (SoC), digital RF processor (DRP), design for testability (DfT), design for manufacturability (DfM), built-in self-testing (BiST), soft specifications

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A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

Cited by 78 publications

References 10 publications

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Built-In Measurements in Low-Cost Digital-RF Transceivers

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