A 2.4-GHz/5-GHz Low Power Pulse Swallow Counter in 0.18-¿m CMOS Technology

Subthreshold Frequency Synthesis for Medical Implantable Transceivers

“…A summary of the power consumption for each of the major blocks is given in Table 5. (Kuo & Wu, 2006) 2400 and 5000 1.8 2.6 1.08 (0.18µm) (Kuo & Weng, 2009) 5141 to 5860 1.5 4.8 0.934 (0.18µm) (Lei et al, 2009) 500 to 3500 1.8 3.01 0.86 (0.18µm) (Pan et al, 2008) 1600 1.2 0.475 0.296 (0.18µm) (Kim et al, 2008) 3000 1.5 3.58 1.19 (0.18µm) (Zhang et al, 2009) 1700 1.5 3.2 1.88 (0.18µm) (Zhang et al, 2006) 440 1.8 0.54 1.23 (0.18µm) In order to perform the required function, the CLR signal is tied to the positive supply and the PRE signal is tied to the negative supply. The block diagram of the PDF is shown in Fig.…”

“…The Pulse and Swallow counters in the programmable frequency divider are programmed to their initial value by clearing and presetting the D flip-flops, each corresponding to a bit in the control word. Previously proposed low power programmable frequency dividers and phase/frequency detectors were implemented using true single-phase clocked (TSPC) logic (Lee et al, 1999), (Kuo & Wu, 2006), (Kuo & Weng, 2009), (Lei et al, 2009). Although TSPC logic occupies small silicon area, it suffers from drawbacks such as generation of switching noise, charge leakage at low frequencies, and requires rail-to-rail input signal swing (Luong, 2004).…”

A Gigahertz Digital CMOS Divide-by-N Frequency Divider Based on a State Look-Ahead Structure

“…The key emphasis of (26) is that the delay is bounded by the module-1 for counter widths greater than 64-bits. In general, for very large counter widths (a module-1 size greater than 5 bits), further enhancements can be made using our topology as a subtopology of a complete structure.…”

“…The programmable swallow counter [26,37,52] provides a wide variety of dividing ratios, which makes this counter amenable to multi-system applications. These counters are composed of an N -bit programmable counter, an S-bit swallow counter, and a P -bit prescaler counter, which results in an input frequency (F in ) to output frequency (F out ) relationship of F out = (NP + S)F in .…”

“…Using this mechanism, they showed high-frequency operation regardless of the divider size. Kuo and Wu [26] noted that the control logic must be properly initialized during each reload in order to avoid circuit failure and alleviated this issue using an external signal, which was ORed with the restart signal to ensure the reload signal is active high, at the cost of losing the first clock cycle after every reload. However, the control block architecture is an irregular asynchronous structure that is unsuitable for wide-range programmable counters and these frequency dividers suffer from pipeline latency as well as long delays associated with the ripple counter and accumulated jitter.…”