A 2- 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop

Wu, Jiangchao; Law, Man‐Kay; Mak, Pui-In; Martins, Rui P.

doi:10.1109/tcsii.2015.2504944

Cited by 37 publications

(15 citation statements)

References 10 publications

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“…The proposed RRL is composed of a fully differential Miller integrator, which uses MOS-bipolar pseudoresistors and capacitors in the negative feedback loop. (2,8,10) The transfer function of the Miller integrator is expressed as Fig. 3.…”

Section: Chopper-stabilized Resistive Readout Ic With Rrlmentioning

confidence: 99%

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Low-Noise Chopper-Stabilized Resistive Readout Integrated Circuit with Ripple Rejection Loop

2017

Sensors and Materials

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Resistive sensors are widely used in many applications such as pressure sensors, touch screens, body composition analyzers, and acceleration sensors. Chopper stabilization is an effective solution to reduce DC offset and low-frequency flicker noises. In the demodulation stage of chopper stabilization, a high-order low-pass filter, which occupies a large area, is generally required to attenuate the up-converted DC offset and low frequency noises or "ripples". We propose a lownoise chopper-stabilized resistive readout integrated circuit (IC) with a ripple rejection loop (RRL). When the RRL operates, the modulated ripple is demodulated to the baseband. The demodulated ripple is integrated using a Miller integrator. The output of the integrator is chopped and fedback negatively to the input of the instrumentation amplifier (IA). The Miller integrator is implemented using MOS-bipolar pseudoresistors and feedback capacitors to achieve high CMRR, high DC rejection, and a small circuit size. The chip is fabricated using a 0.18-µm complementary metaloxide-semiconductor (CMOS) process with an active area of 1.8 mm 2 . The power consumption is 827 μW at 3.3 V supply. The input referred noise is measured at 0.37 μVrms in the frequency band of 1-200 Hz.

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Section: Chopper-stabilized Resistive Readout Ic With Rrlmentioning

confidence: 99%

“…(2,8) The proposed IC uses the chopper stabilization technique to reduce DC offset and low-frequency flicker noise. The RRL effectively reduces the ripple voltage and DC offset while taking up only a small area.…”

Section: Introductionmentioning

confidence: 99%

Low-Noise Chopper-Stabilized Resistive Readout Integrated Circuit with Ripple Rejection Loop

2017

Sensors and Materials

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“…One issue with amplification is the overlap of these signals with 1/f noise. To mitigate the effect of 1/f noise, a chopping technique can be applied for instrumentation amplifiers (IAs) [3][4][5][6][7][8][9][10][11][12]. Another issue is the electrode offset voltage V EOS generated at the tissue-electrode interface by electrochemical effects.…”

Section: Introductionmentioning

confidence: 99%

“…In [7], a dual DSL which consists of coarse and fine DSLs reduces the value of C hp from 670 to 100 fF. In [8], the output of a DSL is connected to the cascode branch of a transconductor to mitigate the charge dividing effect. Nevertheless, these CCIAs consume 3.48 µW [7] and 2.13 µW [8], which results in relatively high PEFs of 18.3 and 10.5 (over a 10-kHz bandwidth), respectively.…”

Section: Introductionmentioning

confidence: 99%

A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

Pham

Nguyen

et al. 2020

Sensors

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To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

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“…First of all, it must be able to cope with the effects of large skin-electrode impedance changes on the signal, usually by a pre-amplifier with very high input-impedance to minimize signal attenuation and degeneration [5]. Chopper-stabilized amplifier is a popular front-end topology for ECG monitoring and neural recording [6][7][8][9][10], as the chopper technique is an effective way to suppress low-frequency flicker noise of the amplifier [11]. However, chopping reduces the DC input impedance of the amplifier because the passive mixer at the input together with the input capacitor forms a switched-capacitor resistance.…”

Section: Introductionmentioning

confidence: 99%

Low Noise, High Input Impedance Digital-Analog Hybrid Offset Suppression Amplifier for Wearable Dry Electrode ECG Monitoring

Wang

Wei

et al. 2020

Electronics

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The portable real-time electrocardiogram (ECG) is a convenient and promising electronic device for cardiovascular diseases patients. However, unlike wet gel electrodes in traditional clinical applications, dry electrodes are competent for comfortable long-time wearing and can prevent skin ulceration. Its ultra-high source impedance and electrode offset (EOS) make traditional chopper amplifiers with low input impedance and limited EOS range difficult to apply to this area. To overcome these challenges, this paper proposes a novel chopper amplifier topology. This architecture includes a gain control loop, a ripple reduction loop, and a DC-servo loop (DSL). The proposed sampling input stage and digital-analog hybrid DSL are employed to boost input impedance and extend the EOS handing range. Designed with a 0.18 µm 1P6M 1.8 V CMOS salicide process, the proposed chopper capacitively coupled instrumentation amplifier achieves an ultra-high input impedance of 120 GΩ (<0.05 Hz) or 2.1 GΩ (0.6~250 Hz), an EOS handing range of ±325 mV and a low noise of 1.9 μVrms at 0.6~250 Hz. It occupies an area of 0.36 mm2 and only consumes a quiescent current of 11 μA.

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A 2- 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop

Cited by 37 publications

References 10 publications

Low-Noise Chopper-Stabilized Resistive Readout Integrated Circuit with Ripple Rejection Loop

Low-Noise Chopper-Stabilized Resistive Readout Integrated Circuit with Ripple Rejection Loop

A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing

Low Noise, High Input Impedance Digital-Analog Hybrid Offset Suppression Amplifier for Wearable Dry Electrode ECG Monitoring

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