A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

Lan, Jingchao; Zhai, Danfeng; Chen, Yongzhen; Ni, Zhekan; Shen, Xingchen; Ye, Fan; Ren, Junyan

doi:10.3390/electronics10243173

Cited by 4 publications

(3 citation statements)

References 40 publications

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“…According to the theory of the autocorrelation principle, there is a linear relationship between the output data of the adjacent two-channel ADC and the sampling interval [11][12][13][14]. By continuously accumulating the output data of the adjacent two-channel ADC, the skew mismatch information according to the adjacent sampling time can be obtained [15][16][17].…”

Section: Autocorrelation Methodsmentioning

confidence: 99%

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A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology

Feng

Chi

et al. 2022

Electronics

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With the great improvement in data transmission rate requirements, the analog-to-digital converter (ADC)-based wireline receiver has received more attention due to its flexible and powerful equalization capability. Time-interleaved ADC (TI-ADC) is the most commonly used architecture in high-speed ADC-based receivers. One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The traditional skew detection and calibration circuits consume substantial power and area of the receiver system. In this article, we propose a novel calibration method using the autocorrelation principle combined with an existing Mueller–Müller clock and data recovery circuit (MM-CDR). This new method reuses the existing error-direction information of the MM-CDR in the ADC-based wireline receiver and combines the autocorrelation principle to obtain the timing mismatch information in the TI-ADC without adding an additional skew deviation extraction circuit, which greatly reduces the area and power consumption. In order to demonstrate the effectiveness and superiority of our skew calibration method, we designed a complete ADC-based wireline receiver circuit using the 28 nm CMOS technology. The simulation results show that our proposed calibration method could obtain 0.193 sensitivity per 1% skew, which was superior to traditional calibration methods. To verify the speed and accuracy of the convergence of our calibration method, the initial skews were set to +0.4 ps, +0.2 ps, −0.59 ps, and 0 ps for our 4 × 8 TI-ADC; the spurious free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) of the ADC were increased from 37.24 dB and 31.28 dB to 48.07 dB and 34.56 dB, respectively, after timing calibration with a 50 fs step. In order to compare the area and power consumption required by different skew calibration methods, we synthesized the expressions of various methods using the 28 nm CMOS technology, and the area and power consumption of our proposed skew calibration loop were 695 μm2 and 0.126 mW, respectively, which were the smallest among these methods.

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Section: Autocorrelation Methodsmentioning

confidence: 99%

“…Electronics 2022, 11, x FOR PEER REVIEW 3 of 14 14]. By continuously accumulating the output data of the adjacent two-channel ADC, the skew mismatch information according to the adjacent sampling time can be obtained [15][16][17].…”

Section: Proposed Cdr-based Timing Calibrationmentioning

confidence: 99%

A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology

Feng

Chi

et al. 2022

Electronics

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“…Several efforts have been made to improve the area-and-power efficiency of pipelined-SAR ADCs, which is critical in a multi-channel application. A popular and effective improvement is to replace the power-hungry op-amps with amplifiers without DC power consumption, such as ringamp [10,11], dynamic amplifiers [12,13], or to use open-loop amplifiers [14,15]. Though these designs significantly reduce the power consumption of RA, they suffer from PVT fluctuations and often rely on complex background calibration.…”

Section: Pipelined-sar Adcmentioning

confidence: 99%

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

Ren

2022

Electronics

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This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. A reference sharing scheme with reduced buffers is proposed to improve area-and-power efficiency, which is essential for multi-channel systems. Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. The prototype ADC is designed in a 0.18-μm process with peripheral circuits integrated, including low-voltage differential signaling (LVDS), bandgap, etc. It achieves a robust and calibration-free performance with 68.25-dB signal to noise and distortion ratio (SNDR) and 82.19-dB spurious-free dynamic range (SFDR), translating into a competitive figure of merit (FoM) of 0.47 pJ/conversion-step among other high-resolution ADCs used in ultrasound applications.

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A 1.5GS/s Single-Channel Pipelined ADC With Large Dither Technique

Jiang,

Wu,

Guo

et al. 2023

2023 8th International Conference on Integrated Circuits and Microsystems (ICICM)

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A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

Cited by 4 publications

References 40 publications

A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology

A Novel Autocorrelation Combined MM-CDR Time-Interleaved ADC Timing Calibration in 28 nm CMOS Technology

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

A 1.5GS/s Single-Channel Pipelined ADC With Large Dither Technique

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