A 2.535 GHz fully integrated Doherty power amplifier in CMOS 65nm with constant PAE in backoff

Abstract

A fully integrated Doherty power amplifier at 2.535 GHz is presented in 65 nm CMOS technology with constant PAE over a 8.75dB backoff. The amplifier has 23.4 dBm output power and both PAE peaks have the same level in 25%. Both sub-amplifiers have a single-ended cascode topology and optimized input and output networks to reduce losses and correctly balance their behavior.I.

Fully integrated Doherty power amplifier electromagnetically optimized in CMOS 65nm with constant PAE in backoff

“…Due to paths parasitic capacitances, some inductors in layout were increased to correct the load matching. To insert the new sized inductors and transistors, the borders and pads of the chip needed to be moved increasing the layout 3.2% related to work [6].…”

“…[5] have small increase in PAE in relation to class AB/B. For a 8 dB power backoff, the designed amplifier presents 6% more PAE than [2], [6], [5] and 16% more PAE than [3], [4]. DPAs in [2], [3], [4], [5] present a big reduction in PAE at that backoff point and the shape of the PAE curve does not represent clearly the DPA characteristic shape.…”

“…This work presents the output power and PAE optimization of the first fully integrated DPA [6] with constant PAE in the backoff. The optimization recovered the designed output power and surpassed the PAE expected level by considering in the optimization the parasites in each path and pad through electromagnetic models.…”

“…Sub-amplifiers output connections were made by a topology that merges a λ/4 transmission line and the L-network matching of both amplifiers. This new topology [6] was used for saving die area by reducing number of inductances in the circuit. Figures Fig.…”

“…Many works aim to fully integrate DPA in a low cost technology [2] [3][4] [5] but the central objective of making a constant PAE between the backoff and the maximum output power has not been achieved yet with fully integration in CMOS technology. This paper proposes the enhancement of the work [6] by modeling electromagnetically all layout paths and pads for re-optimizing the circuit. The objective was to overcome the parasitic losses and to produce the output power determined by the schematic, and to increase the power-added efficiency (PAE) by recovering the optimal load match.…”