A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm²

Abstract

Energy consumption is a dominant constraint on the performance of modern microprocessors and systems-on-chip. Dynamic voltage and frequency scaling (DVFS) is a promising technique for performing "on-the-fly" energy-performance optimization in the presence of workload variability. Effective implementation of DVFS requires voltage regulators that can provide many independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs) [1]. Switched-inductor integrated voltage regulators (IVRs) can enable effective implementation of DVFS, eliminating the need for separate VRMs and reducing power distribution network (PDN) impedance requirements by performing dc-dc conversion close to the load while supporting high peak current densities [2][3]. The primary obstacle facing development of IVRs is integration of suitable power inductors. This work presents an early prototype switched-inductor IVR using 2.5D chip stacking for inductor integration.Figure 23.1.1 shows the complete 2.5D chip stack. A prototype IC, fabricated in IBM's 45nm SOI process, contains buck converter circuitry, decoupling capacitance and a realistic digital load. This IC is flip-chip mounted onto an interposer that holds custom fabricated coupled power inductors for the buck converter while breaking out signals and the 1.8V input power supply to wirebond pads on the perimeter of the interposer. . The pole in both RC low-pass filters is chosen to be below f s so that the steady state amplitude of V REF,I and V FB,I is around 150mV, which gives a small signal feedback gain of ~30V/V and ensures stable loop dynamics. In steady state, V FB,I will slew behind V REF,I and the resultant evaluation of the comparator causes V BRIDGE to closely track V PWM . In the event of a large load current transient, the error in the output voltage, V OUT , will couple across C FB onto V FB,I and the comparator will react immediately to reduce overshoot in V OUT . This fast non-linear response can reduce the required decoupling capacitance on the output voltage [3]. Also residing on the IC is a 64-tile network-on-chip (NoC) consisting of four parallel, heterogeneous, physical network planes with independent frequency domains. The NoC provides realistic load behavior and supports experimentation on supply noise and DVFS. In addition, an artificial load on the IC is capable of generating large current transients with ~2A/100ps slew. A total of 48nF of deep-trench (DT) and thick oxide MOS capacitance decouples V OUT and occupies 0.40mm 2 , while 21nF of DT occupying 0.52mm 2 decouples the 1.8V input supply to compensate for the large PDN impedance.Two sets of four coupled power inductors, shown in Fig. 23.1.3, are fabricated on the silicon interposer such that one terminal of each inductor connects to a pair of V BRIDGE C4 receiving pads, while the opposite terminals are shorted and connected to several pads across the interposer for distribution of V OUT . The inductor top...

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“…Moreover, it supports the fine-grained voltage and frequency management and better power delivery efficiency. There have been attempts to embed voltage regulators on chips to support fine-grained voltage management [9], and a voltage regulator stacked in 2.5D has been demonstrated [10].…”

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