A 2.5Gb/s multi-rate 0.25μm CMOS CDR utilizing a hybrid analog/digital loop filter

Perrott, Michael H.; Huang, Yunteng; Baird, R.T.; Garlepp, B.W.; Zhang, Ligang; Hein, J.P.

doi:10.1109/isscc.2006.1696175

Cited by 5 publications

(5 citation statements)

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“…This phase measurement circuit is similar to that described in [3]. Alternatively, one can use the direct phase-to-digital converters, as described in [4]. In our case, the phase detector and charge pump circuits were made identical to those from the PLL under test to reduce the design efforts [8].…”

Section: B Periodic Phase Samplermentioning

confidence: 99%

On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

Kim

2009

IEEE Trans. Circuits Syst. II

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This brief describes low-cost on-chip measurement circuits for jitter transfer and supply sensitivity of phase-locked loops (PLLs) and delay-locked loops (DLLs). Unlike previous works that measured the frequency-domain responses, the proposed circuits measure the time-domain responses of the PLL/DLL to the periodic disturbances applied to either its input clock phase or its supply voltage. A synchronous sampling technique accurately measures the PLL/DLL's periodic response while suppressing the unrelated noises and interferences via averaging. The synchronous sampler outputs either dc voltage or digital values, making it suitable for low-cost characterization and production tests. The procedure for estimating the frequency-domain transfer functions from the measured time-domain responses is outlined. The jitter transfer and supply sensitivity measurements were demonstrated with a PLL fabricated in 0.13-µm CMOS. Compared with the PLL that occupied 1.1 × 0.46 mm 2 and dissipated 36 mW from a 1.2-V supply, the on-chip measurement circuits occupied only 0.014 mm 2 and dissipated only 2.6 mW. Index Terms-CMOS, jitter transfer function, on-chip measurement, phase-locked loop (PLL), supply sensitivity.

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Section: B Periodic Phase Samplermentioning

confidence: 99%

On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

Kim

2009

IEEE Trans. Circuits Syst. II

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“…Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter [1,2]. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs [3][4][5].A bang-bang phase detector provides a simple interface to the DLF without any inherent static phase offset (SPO) [1,3]. However, it introduces a large phase quantization error that limits the jitter transfer bandwidth, and its nonlinear behavior makes loop dynamics difficult to control.…”

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confidence: 99%

“…However, it introduces a large phase quantization error that limits the jitter transfer bandwidth, and its nonlinear behavior makes loop dynamics difficult to control. A time-to-digital converter (TDC) that is realized using a linear phase detector followed by an ADC could provide fixed gain that enables well-controlled loop dynamics and achieve the desired jitter transfer bandwidth [4,5]. However, it is susceptible to ADC nonidealities that manifest as large SPO, as well as additional power for the ADC.…”

mentioning

confidence: 99%

“…A bang-bang Alexander detector recovers the data without any systematic SPO and generates the early/late information to drive the accumulator in the digital integral path. A decimator allows lower clock frequency operation of the digital circuitry.The PLL proportional path is implemented by directly controlling the DCO with a linear Hogge detector, thus eliminating the non-linearity and quantization error of a bang-bang detector [3] and the need for a high resolution TDC [4,5]. Because, only a 3-level DAC is needed to interface Hogge detector outputs to the oscillator, the circuit realization of the proportional path incurs minimal area and power penalty.…”

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confidence: 99%

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A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery

Yin¹,

Inti²,

Elshazly³

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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A clock and data recovery (CDR) circuit is the key building block in all serial communication systems. A classical CDR is implemented using a Type-2 phaselocked loop (PLL) wherein a passive lead-lag analog loop filter is used to set the loop response. Large capacitors needed to achieve low jitter transfer bandwidth and a highly over-damped response to reduce jitter peaking prohibit monolithic integration of the analog loop filter [1,2]. Digital loop filters (DLFs) that are robust to process and temperature variations have recently emerged as an alternate solution to implementing fully integrated CDRs [3][4][5].A bang-bang phase detector provides a simple interface to the DLF without any inherent static phase offset (SPO) [1,3]. However, it introduces a large phase quantization error that limits the jitter transfer bandwidth, and its nonlinear behavior makes loop dynamics difficult to control. A time-to-digital converter (TDC) that is realized using a linear phase detector followed by an ADC could provide fixed gain that enables well-controlled loop dynamics and achieve the desired jitter transfer bandwidth [4,5]. However, it is susceptible to ADC nonidealities that manifest as large SPO, as well as additional power for the ADC. In this paper, the advantages of bang-bang and linear phase detectors are combined in a digital CDR to achieve error-free operation and fixed jitter transfer bandwidth, independent of input jitter amplitude. The CDR decouples the tradeoff between jitter generation and jitter transfer by eliminating the phase quantization error in the proportional path, which allows wide loop bandwidth to suppress DCO phase noise and frequency quantization error. Figure 25.3.1 illustrates the proposed CDR architecture. It consists of a frequency-locking loop (FLL) and a Type-2 digital PLL. At start-up, the FLL drives the DCO frequency to within 500ppm of any incoming data rate in a 0.5 to 3.2Gb/s range. The PLL consisting of a linear proportional path and a bang-bang digital integral path achieves frequency and phase lock. A bang-bang Alexander detector recovers the data without any systematic SPO and generates the early/late information to drive the accumulator in the digital integral path. A decimator allows lower clock frequency operation of the digital circuitry.The PLL proportional path is implemented by directly controlling the DCO with a linear Hogge detector, thus eliminating the non-linearity and quantization error of a bang-bang detector [3] and the need for a high resolution TDC [4,5]. Because, only a 3-level DAC is needed to interface Hogge detector outputs to the oscillator, the circuit realization of the proportional path incurs minimal area and power penalty. The infinite DC gain of the digital accumulator forces the bangbang PD to its metastability point and locks the recovered clock (RCK) to the incoming data without any static phase offset. As a result, any offset in the Hogge detector causes periodic modulation at the data rate and introduces a fixed frequency offset and ripple in the pro...

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