A 2.5mW Low-Power Dual VCO Quantizer for ∑-∆ Modulator in 0.09μm CMOS

Chavan, Arunkumar P; Ranasubhe, Sachin Manohar; Rohit, N; Aradhya, H. V. Ravish

doi:10.1109/vlsidcs47293.2020.9179869

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2023

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“…In [11] authors developed a ring oscillator based on the current source this design consumes less power but lacks in frequency tuning. In [12] author developed a design of current starved VCO that dissipates large power.…”

Section: Introductionmentioning

confidence: 99%

Design of 5.1 GHz ultra-low power and wide tuning range hybrid oscillator

Chavan

Aradhya

2023

IJECE

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<p><span lang="EN-US">The objective of the proposed work is to demonstrate the use of a hybrid approach for the design of a voltage-controlled oscillator (VCO) which can lead to higher performance. The performance is improved in terms of the tuning range, frequency of oscillation, voltage swing, and power consumption. The proposed hybrid VCO is designed using an active load common source amplifier and current starved inverter that are cascaded alternatively to achieve low power consumption. The proposed VCO achieves a measured phase noise of -74 dBc/Hz and a figure of merit (FOM) of -152.6 dBc/Hz at a 1 MHz offset when running at 5.1 GHz frequency. The hybrid current starved-current starved VCO (CS-CS VCO) consumes a power of 289 µW using a 1.8 V supply and attains a wide tuning range of 96.98%. Hybrid VCO is designed using 0.09 µm complementary metal–oxide–semiconductor (CMOS) technology. To justify the robustness, reliability, and scalability of the circuit different corner analysis is performed through 500 runs of Monte-Carlo simulation.</span></p>

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Section: Introductionmentioning

confidence: 99%