2017 Symposium on VLSI Circuits 2017
DOI: 10.23919/vlsic.2017.8008502
|View full text |Cite
|
Sign up to set email alerts
|

A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
2
1

Citation Types

0
6
0

Year Published

2021
2021
2024
2024

Publication Types

Select...
5

Relationship

3
2

Authors

Journals

citations
Cited by 5 publications
(6 citation statements)
references
References 3 publications
0
6
0
Order By: Relevance
“…The chosen-input attack scenarios considered in this paper have been used in power analysis against some implementations of block ciphers (e.g., DES [12] and AES [13]). R RC [1] p c R RC [2] R RC [3] R RC [4] R RC [5] R RC [6] R RC [7] R RC [8] R RC [9] R RC [10] S M S -1 -1 -1 -1 -1 -1 1 2 3 4 5 6 7 8 9 Against DES software, previous attacks, such as those in [14], [15], and [16], have overcome some masking methods by fixing the inputs in a particular manner. Against an AES software implementation in which the inner rounds were not protected, Lu et al [17] demonstrated a first-and second-order differential power analysis (DPA) attack that exploits some inner round intermediate values by fixing certain parts of the inputs.…”
Section: Preliminaries and Related Workmentioning
confidence: 99%
See 3 more Smart Citations
“…The chosen-input attack scenarios considered in this paper have been used in power analysis against some implementations of block ciphers (e.g., DES [12] and AES [13]). R RC [1] p c R RC [2] R RC [3] R RC [4] R RC [5] R RC [6] R RC [7] R RC [8] R RC [9] R RC [10] S M S -1 -1 -1 -1 -1 -1 1 2 3 4 5 6 7 8 9 Against DES software, previous attacks, such as those in [14], [15], and [16], have overcome some masking methods by fixing the inputs in a particular manner. Against an AES software implementation in which the inner rounds were not protected, Lu et al [17] demonstrated a first-and second-order differential power analysis (DPA) attack that exploits some inner round intermediate values by fixing certain parts of the inputs.…”
Section: Preliminaries and Related Workmentioning
confidence: 99%
“…Figure 7 shows an example of power traces and a CPA result obtained from the FPGA implementation. c R K RC [3] R RC [4] R RC [5] R RC [6] R RC [7] R RC [8] R RC [9] R RC [10] RC [11] K' wh [4] R RC [5] R RC [6] R RC [7] R RC [8] R RC [9] R RC [10] wh…”
Section: Experimental Validationmentioning
confidence: 99%
See 2 more Smart Citations
“…Color versions of one or more figures in this article are available at https://doi.org/ level performance for more ubiquitous leverage of cryptography [7]- [9]. On the other hand, public-key ciphers realize the higher order security functionality demanded in IoT evolvements [10]- [11].…”
Section: Introductionmentioning
confidence: 99%