A 2.6 e-rms Low-Random-Noise, 116.2 mW Low-Power 2-Mp Global Shutter CMOS Image Sensor with Pixel-Level ADC and In-Pixel Memory

Seo, Min-Woong; Chu, Myonglae; Jung, Hyun-Yong; Kim, Suksan; Song, Joonho; Lee, Junan; Kim, Sung-Yong; Lee, Jongyeon; Byun, Seung-Woo; Bae, Daehee; Kim, Minkyung; Lee, Gwi-Deok; Shim, Heesung; Um, Changyong; Kim, Changhwa; Baek, In-Gyu; Kwon, Doowon; Kim, Hongki; Choi, Hyuksoon; Go, Jonghyun; Ahn, Jin-Hyun; Lee, Jaekyu; Moon, Cheol; Lee, Kyu Pil; Kim, Hyoung-Sub

doi:10.23919/vlsicircuits52068.2021.9492357

Cited by 17 publications

(4 citation statements)

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“…The fabricated top and bottom chips have been bonded and then it is packaged for the evaluation. All functions and sensor performances have been successfully evaluated and demonstrated [6]. Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors

Jung¹,

Myonglae²,

Min-Woong³

et al. 2022

Self Cite

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A Low-power and low-noise digital pixel sensor (DPS) is presented in this paper. To design and analyze the random noise (RN) of the developed DPS, especially, we utilize a novel simulation method called transient-based AC noise simulation (TBAS) which can effectively help to estimate the noise components of the low-powered single-slope (SS) analog-to-digital converter (ADC).Based on this noise analysis, the high performance DPS has been successfully designed and demonstrated.

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Section: Measurement Resultsmentioning

confidence: 99%

Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors

Jung¹,

Myonglae²,

Min-Woong³

et al. 2022

Self Cite

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“…It may be noted that typical DVS pixels are larger due to the inclusion of a capacitive feedback difference amplifier. The overall system can be fabricated by a wafer-to-wafer bonding process using pixel-level hybrid Cu2Cu interconnects (Kagawa et al, 2016 ; Miura et al, 2019 ; Seo et al, 2021 ). Each DVS pixel has two Cu2Cu interconnects for its ON and OFF-channel, respectively.…”

Section: P 2 M Circuit Implementationmentioning

confidence: 99%

Neuromorphic-P2M: processing-in-pixel-in-memory paradigm for neuromorphic image sensors

Kaiser

Datta

Wang

et al. 2023

Front. Neuroinform.

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Edge devices equipped with computer vision must deal with vast amounts of sensory data with limited computing resources. Hence, researchers have been exploring different energy-efficient solutions such as near-sensor, in-sensor, and in-pixel processing, bringing the computation closer to the sensor. In particular, in-pixel processing embeds the computation capabilities inside the pixel array and achieves high energy efficiency by generating low-level features instead of the raw data stream from CMOS image sensors. Many different in-pixel processing techniques and approaches have been demonstrated on conventional frame-based CMOS imagers; however, the processing-in-pixel approach for neuromorphic vision sensors has not been explored so far. In this work, for the first time, we propose an asynchronous non-von-Neumann analog processing-in-pixel paradigm to perform convolution operations by integrating in-situ multi-bit multi-channel convolution inside the pixel array performing analog multiply and accumulate (MAC) operations that consume significantly less energy than their digital MAC alternative. To make this approach viable, we incorporate the circuit's non-ideality, leakage, and process variations into a novel hardware-algorithm co-design framework that leverages extensive HSpice simulations of our proposed circuit using the GF22nm FD-SOI technology node. We verified our framework on state-of-the-art neuromorphic vision sensor datasets and show that our solution consumes ~2× lower backend-processor energy while maintaining almost similar front-end (sensor) energy on the IBM DVS128-Gesture dataset than the state-of-the-art while maintaining a high test accuracy of 88.36%.

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“…The first segment is data acquisition [1,2], the second segment includes audio and voice applications [3,4], and the third segment includes industrial measurements [5][6][7]. Subsequently, there is control or feedback digital control, and the last segment involves very fast applications such as high-frequency devices [8,9], video processing [10], etc. [11,12].…”

Section: Introductionmentioning

confidence: 99%

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors

Sokol,

Galajda,

Saliga

et al. 2024

Sensors

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The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter’s own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of −3.3 V.

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A 2.6 e-rms Low-Random-Noise, 116.2 mW Low-Power 2-Mp Global Shutter CMOS Image Sensor with Pixel-Level ADC and In-Pixel Memory

Cited by 17 publications

References 0 publications

Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors

Design and analysis on low-power and low-noise single slope ADC for digital pixel sensors

Neuromorphic-P2M: processing-in-pixel-in-memory paradigm for neuromorphic image sensors

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors

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