A 2.7 V only 8 Mb×16 NOR flash memory

Chen, J.C.; Kuo, Tzu-Yuan; Cleveland, L.; Chung, Chiu-Chiao; Leong, N.; Kim, Y.K.; Akaogi, T.; Kasa, Yasushi

doi:10.1109/vlsic.1996.507759

Cited by 15 publications

(10 citation statements)

References 3 publications

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“…The clock generator proposed in this paper produces 4 phase clocks; each clock (CLK 1 , CLK 2 , CLK 3 , and CLK 4 ) has a certain fixed delay, unlike other references [9][10][11][12]16].…”

Section: Reconfigurable Charge Pump Architecturementioning

confidence: 99%

“…2 Additionally, since these switches will have small parasitic capacitance and resistance, they will have minimal impact on the charge pump operation, and additional area will not be needed, in terms of chip area. The charge pump core proposed in this paper does not suffer from voltage drop due to the threshold voltage, body-effect and gate oxide breakdown, as compared to the conventional Dickson charge pump [6][7][8][9][10][11][12][13][14].…”

Section: Reconfigurable Charge Pump Architecturementioning

confidence: 99%

“…Since MN 3 is off at time T1, the charge on N 3 (a) The Clock Generator in the proposed Clock Driver has delay cells that generate 4 phase clocks, so that the charge transfer in the reverse direction between adjacent stages can be blocked, during transition in each clock. The proposed Clock Generator produces 4-phase clocks, by adding only delay to each clock, and the structure is simple, against the previous complicated 4-phase clock generators [9][10][11][12]16]. Fig.…”

Section: Building Blocksmentioning

confidence: 99%

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A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

Park¹,

Jang²,

Cho³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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“…The clock generator proposed in this paper produces 4 phase clocks; each clock (CLK 1 , CLK 2 , CLK 3 , and CLK 4 ) has a certain fixed delay, unlike other references [9][10][11][12]16].…”

Section: Reconfigurable Charge Pump Architecturementioning

confidence: 99%

Section: Reconfigurable Charge Pump Architecturementioning

confidence: 99%

Section: Building Blocksmentioning

confidence: 99%

See 1 more Smart Citation

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

Park¹,

Jang²,

Cho³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

“…It relaxes the condition of clock phases compared to the 4-phase clock schemes [2,3]. The dclko fall should come after clko fall in order to turn on the CTM (M 1) only after Nt1 voltage goes higher than Nt2.…”

Section: Proposed Circuitsmentioning

confidence: 99%

“…An important issue in those applications is high voltage generation with high current drivability in the low supply voltage. Numerous charge pump (CP) circuits, mostly based on Dickson's CP [1], have been proposed to improve voltage efficiency and current drivability [2,3]. However, they require a differential circuit structure or the 4-phase clocks which industries may not prefer due to design burden [4].…”

Section: Introductionmentioning

confidence: 99%

New charge pump circuits for high output voltage and large current drivability

Chung

Shin

2009

IEICE Electron. Express

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New charge pump circuits with high current drivability in low supply voltage are proposed. It generates a large gate-overdrive voltage of charge transfer MOSFET by pulling down the gate node voltage by deliberate leakage. A proper clock circuit is also presented to effectively suppress accompanied loss effects. The characteristics of the proposed charge pumps were investigated through simulation and measurement of fabricated circuit. The measurement result shows an excellent pumping performance especially under the condition of heavy load current.

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Charge Pump Circuits for Low‐voltage Applications

Moisiadis

Bouras²,

Arapoyanni

2001

VLSI Design

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In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several cross-connected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5–8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.

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A 2.7 V only 8 Mb×16 NOR flash memory

Cited by 15 publications

References 3 publications

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

A Wide Output Range, High Power Efficiency Reconfigurable Charge Pump in 0.18 mm BCD process

New charge pump circuits for high output voltage and large current drivability

Charge Pump Circuits for Low‐voltage Applications

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