A 2.7μW/MIPS, 0.88GOPS/mm² distributed processor for implantable brain machine interfaces

Abstract

Abstract-This paper presents a scalable architecture in 0.18 µm CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7 µW/MIPS with a total chip area of 6.2 mm 2 . This configuration executes 1024 instructions on each core at 20 MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.

A 0.016 mm2 12 b $\Delta \Sigma $ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays

“…Preliminary efforts to realize the system in Fig. 1 are presented in [14] and the circuits proposed here are improved to achieve better power efficiency as part of a larger reconfigurable neural recording system [15]. This system uses an array of miniaturised ADCs that distributes the digital processing over many parallel segments leading to lower clock frequencies and better efficiency opposed to demanding a single high frequency ADC and digital core.…”