2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)
DOI: 10.1109/vlsic.2002.1015077
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A 2.9ns random access cycle embedded DRAM with a destructive-read

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Cited by 11 publications
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“…There is no energy consumption in the pre-sense stage. While in the post-sense stage, the sense amplifier senses and amplifies ∆V to VDD, i.e., charging the BL to VDD and discharging the BLB to ground [27]. Theoretically, the energy consumption is (VDD 2 C b )/2 for both the logic 0 and 1 states.…”
Section: Pre-sense and Post-sense Stagementioning
confidence: 99%
“…There is no energy consumption in the pre-sense stage. While in the post-sense stage, the sense amplifier senses and amplifies ∆V to VDD, i.e., charging the BL to VDD and discharging the BLB to ground [27]. Theoretically, the energy consumption is (VDD 2 C b )/2 for both the logic 0 and 1 states.…”
Section: Pre-sense and Post-sense Stagementioning
confidence: 99%