A 2&amp;#x00D7;13-bit all-digital I/Q RF-DAC in 65-nm CMOS

Alavi, Morteza S.; Voicu, George; Staszewski, Robert Bogdan; Vreede, L.C.N. de; Long, John R.

doi:10.1109/rfic.2013.6569551

Cited by 16 publications

(8 citation statements)

References 6 publications

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“…7b. The output impedance of the SCPA can be estimated by the parasitic resistance of the MOS devices R on , the capacitance of C u and the parasitic capacitances C p as shown in 20 heft 1.2018 [2] is that the output impedance SCPA Zout is independent of the number of ON and OFF slices and the MN does not need to be tuned.…”

Section: Digital Power Amplifier Based Transmittermentioning

confidence: 99%

Integration solutions for reconfigurable multi-standard wireless transceivers

Kale

Batistell

Popuri

et al. 2018

Elektrotech. Inftech.

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This article presents an overview of modern integration concepts for receiver, transmitter and duplexer architectures. Based on innovative design techniques, a system-in-package integrated RF transceiver architecture is proposed as a low-cost low-power alternative to traditional multi-standard transceivers. The proposed transceiver architecture unites advantages of a sub-sampling receiver with tunable low noise amplifier (LNA), a high-efficiency digital power amplifier and an integrated duplexer with on-package passive components in order to fulfill the more and more stringent requirements for wireless systems. In addition to the transceiver architecture, measurement results of building blocks are presented. A LNA circuit implemented in 65 nm CMOS technology provides a continuously tunable-gain (3-23 dB) and a tunable frequency band (4.5 GHz-5.5 GHz) with noise figure of 2 dB and IIP 3 of −6.5 dBm at the highest gain. A high Q-factor, on-package transformer, implemented in a core-less 3-metal layer system-in-package substrate, presents a coupling factor of 0.6 and a Q-factor of approximately 30. This provides a low-cost, high-performance alternative solution to integrated matching networks and duplexers. IntroductionModern wireless transceivers require multi-band and multi-standard operation, which leads to complex, bulky and power hungry implementations. An architecture for state-of-the-art multi-standard transceiver is shown in Fig. 1, where several transmitter (TX) and receiver (RX) chains are required in order to fulfill specifications for wireless standards.With the evolution of wireless systems, even more communication standards are being proposed while maintaining backward compatibility, therefore, cost and complexity of RF transceivers tend to increase. For high-performance communication standards, external off-chip components with optimized performance such as duplexer filter and power amplifier (PA), are necessary to satisfy ever-growing standard requirements. On the contrary, for low-performance battery operated applications such as Internet of things (IoT), lowpower and low-cost implementations are desired.This article presents a set of innovative design concepts, for receivers, transmitters and system-in-package (SiP) integration, which provides reconfigurability, wide frequency operation, higher power efficiency and low-cost. Based on the presented concepts, an RF transceiver architecture shown in Fig. 2 is proposed. The RX chain is based on a tunable active-balun LNA and a sub-sampling down-

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Section: Digital Power Amplifier Based Transmittermentioning

confidence: 99%

Integration solutions for reconfigurable multi-standard wireless transceivers

Kale

Batistell

Popuri

et al. 2018

Elektrotech. Inftech.

View full text Add to dashboard Cite

show abstract

“…In the first class, upconversion is realized with the "series mixing" approach shown in Fig. 11(a): a separate switch driven by the LO signal is connected in series with the data switch and the current source (CS) [8], [9], [11], [40], [41]. The second class utilizes the "logic mixing" approach shown in Fig.…”

Section: Rf Front-endmentioning

confidence: 99%

“…Each of the 28 mismatch-shaping encoder outputs is synchronized to the LO and separately upconverted through a logic circuit clocked at 2f c , which generates two pseudo-differential outputs c P and c N with 50% duty-cycle. In order to avoid cross-interaction between the I and Q paths, it is desirable to use 25% dutycycling [11], [40], [42]. This can be achieved by performing a final AND with the 2LO signal before the conversion cell [42].…”

Section: Rf Front-endmentioning

confidence: 99%

All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise

Roverato

Kosunen

Cornelissens³

et al. 2017

IEEE J. Solid-State Circuits

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We present the first all-digital LTE transmitter using programmable digital attenuation of RX-band noise. The system is architectured to fully exploit the speed and low cost of DSP logic in deep-submicron CMOS processes, without increasing at all the design effort of the RF circuitry. To achieve SAWless operation, the transmitter uses digital bandpass delta-sigma modulation and mismatch-shaping to attenuate the DAC noise at a programmable duplex distance. These functions can be implemented entirely within DSP, thus taking advantage of the standard digital design methodology. Furthermore, the fully digital RX-band noise shaping significantly relaxes the performance requirements on the RF front-end. Therefore, 10 bits of resolution for the D/A conversion are sufficient to achieve-160 dBc/Hz out-of-band noise, without need for digital predistortion, calibration or bulky analog filters. The transmitter was fabricated in 28nm CMOS, and occupies only 0.82 mm 2. Besides low outof-band noise, our system also demonstrates state-of-art linearity performance, with measured CIM3/CIM5 below-67 dBc, and ACLR of-61 dBc with LTE20 carrier. The circuit consumes 150 mW from 0.9/1.5V supplies at +3 dBm output power.

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“…Other purely digital solutions are for example all digital IQ modulation [13], [14] and all digital PLLs [15], [16]. These developments have led to the concept of RFDACs [17]- [21] with possible resolution enhancement in combination with RF PWM [21].…”

Section: Introductionmentioning

confidence: 99%

Predistortion of Digital RF PWM Signals Considering Conditional Memory

Seebacher

Singerl

Schuberth

et al. 2015

IEEE Trans. Circuits Syst. I

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The trend in transmitter systems is to move the digital domain closer towards the antenna using digital modulators and drivers to reduce circuit complexity and to save power. A common assumption made is that they are capable of generating ideal pulses and thus do not suffer from analog imperfections. But the output signals of real drivers for high frequency operation are not perfectly rectangular anymore, which leads to distortion lowering the signal quality. In this paper the general properties of high frequency digital driver circuits operating at 2.6 GHz are analyzed and the impact of the different effects is presented. The predistortion of such drivers in the context of digital discrete time RF PWM modulators is studied. It has been found that conventional sample based predistortion can only correct the driver nonlinearity from 29 dBc to 49 dBc for the example considered using a 40 MHz bandwidth signal at 2.6 GHz. Therefore a special predistortion scheme considering the impact of pulses adjacent to the other samples is proposed. The mitigation of effects due to the discrete time nature of the signal is considered and discussed in detail. The capabilities of the proposed predistortion scheme are verified by extensive simulations as well as by measurements. By applying the proposed predistortion concept the spectral quality can be further improved to 66 dBc. In addition different scenarios with limited resolution and a carrier frequency offset are analyzed.

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A 2×13-bit all-digital I/Q RF-DAC in 65-nm CMOS

Cited by 16 publications

References 6 publications

Integration solutions for reconfigurable multi-standard wireless transceivers

Integration solutions for reconfigurable multi-standard wireless transceivers

All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise

Predistortion of Digital RF PWM Signals Considering Conditional Memory

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