1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC 1996
DOI: 10.1109/isscc.1996.488550
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A 2 ns zero wait state, 32 kB semi-associative L1 cache

J. Covino
1
,
D. C. Evans
2
,
A. Roberts
3
et al.
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