A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells

Liang, Che-Fu; Liu, Shen-luan

doi:10.1109/isscc.2008.4523138

Cited by 11 publications

(19 citation statements)

References 4 publications

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“…The proposed BMCDR is superior to others in jitter performance. Considering jitter in UI units, the jitter in the proposed BMCDR at 2.5 Gb/s is reduced by 45% and 69% compared with the half-rate BMCDR in [7] and the full-rate BMCDR in [10], respectively. These results demonstrate the effectivenesss of the proposed techniques for enhancing the jitter performanceand reducing frequency offset.…”

Section: Resultsmentioning

confidence: 99%

“…Ideally, the half-rate operation of the GVCO increases the timing margin of the data recovery and the digital frequency calibration twice. For half-rate operation in BMCDRs, dual edge detection schemes have been introduced in [7,8,9]. In [10], a digital frequency calibration technique without using a local reference clock was introduced to reduce the jitter induced by the frequency offset at the expense of an additional digital phase detector.…”

Section: Introductionmentioning

confidence: 99%

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A low-jitter BMCDR for half-rate PON systems

Yoon

Hong

Jung

et al. 2017

IEICE Electron. Express

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This letter presents a 2.5 Gb/s half-rate burst-mode clock and data recovery (BMCDR) with enhanced jitter performance. Compared to conventional half-rate BMCDRs, the proposed work uses a single loop gated voltage controlled oscillator (GVCO) to minimize the timing mismatch. And the GVCO has only one gated delay cell to improve jitter performances. In addition, a tri-state phase detector for digital frequency calibration is also proposed in this letter to further reduce jitter caused by the frequency offset between the input data and the GVCO free running clock. The fabricated chip in a 110 nm CMOS technology occupies the area of 0.08 mm 2 . The proposed BMCDR consumes 29 mW with the measured peak to peak jitter of 17.8 ps p-p (0.022 UI p-p ).

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A low-jitter BMCDR for half-rate PON systems

Yoon

Hong

Jung

et al. 2017

IEICE Electron. Express

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show abstract

“…Clock and data recovery (CDR) circuits have been very popular in wireline applications including optical transceivers, backplane interconnections, chip-tochip inter-connects [1]. Even in wireless on-off keying communication systems, they may become attractive to obtain jitter-less gigabit data links.…”

Section: Introductionmentioning

confidence: 99%

A 3.125-to-22-Gb/s multi-rate clock and data recovery using voltage-regulated active filter

Kim

Xiao

Choi

et al. 2014

IEICE Electron. Express

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This letter presents a multi-rate clock and data recovery circuit realized in a standard 65-nm CMOS technology, which operates from 3.125 Gb/s to 22 Gb/s. In order to cover the wide frequency range, a modified four-stage differential ring VCO is exploited, which provides not only the fast tracking ability from its coarse tuning, but also the precise tra cking from its fine tuning. Also, a voltage-regulated active filter is employed to reduce the ripples of the VCO control voltages. It helps to fasten the lock-in time of the proposed CDR circuit and improve the jitter characteristics against PVT variations. Measurements reveal that the CDR chip demonstrates very wide capture range of 3.125 ∼ 22 Gb/s, 3.3 ps ,rms data jitter at 20 Gb/s, and 112-mW power dissipation from a single 1.2-V supply. The chip core occupies the area of 0.12 mm 2 only.

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“…For the burst-mode applications such as passive optical network (PON) [1,2], the CDR circuit in the receiver must lock to each burst data packet very quickly. In a PON system, the optical line termination (OLT) receives data packets from various optical network units (ONUs) and these data packets have different phase and amplitude, so immediate clock extraction and data retiming in the CDR circuit is necessary.…”

Section: Introductionmentioning

confidence: 99%