A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications

Yamada, Y.; Uchiyama, Masato; Jobashi, M.; Koizumi, Toru; Tamai, Takanori; Sato, Nobuhiro; Tanabe, Jun; Kimura, Kozo; Ojima, Yoshinari; Murakami, Ryusuke; Yoshikawa, Takashi; Sano, Tsuyoshi; Tanabe, Yoshinori; Ishigaki, Yutaro; Hosoda, Soichiro; Hyuga, Fumihiko; Moriya, Akio; Hada, Ryuji; Masuda, Atsushi

doi:10.1109/jssc.2019.2951391

Cited by 5 publications

(2 citation statements)

References 12 publications

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“…Beyond the hardware architecture, there are different methods which are related to ANNs based on the application, such as convolutional neural networks (CNNs), recurrent neural networks (RNNs) and multilayer perceptrons (MLPs)-based networks. Since our priority is energy efficiency, we focus on MLPs, which provide better energy scaling [ 27 , 49 ]. Each layer that comprises MLP has a computational workload, which is composed of relatively basic operations, i.e., multiplication, addition, and activation.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks

Nojehdeh

Altun

2023

Circuits Syst Signal Process

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In this paper, we explore efficient hardware implementation of feedforward artificial neural networks (ANNs) using approximate adders and multipliers. Due to a large area requirement in a parallel architecture, the ANNs are implemented under the time-multiplexed architecture where computing resources are re-used in the multiply accumulate (MAC) blocks. The efficient hardware implementation of ANNs is realized by replacing the exact adders and multipliers in the MAC blocks by the approximate ones taking into account the hardware accuracy. Additionally, an algorithm to determine the approximate level of multipliers and adders due to the expected accuracy is proposed. As an application, the MNIST and SVHN databases are considered. To examine the efficiency of the proposed method, various architectures and structures of ANNs are realized. Experimental results show that the ANNs designed using the proposed approximate multiplier have a smaller area and consume less energy than those designed using previously proposed prominent approximate multipliers. It is also observed that the use of both approximate adders and multipliers yields, respectively, up to 50% and 10% reduction in energy consumption and area of the ANN design with a small deviation or better hardware accuracy when compared to the exact adders and multipliers.

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Section: Introductionmentioning

confidence: 99%

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks

Nojehdeh

Altun

2023

Circuits Syst Signal Process

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“…Many energy-efficient hardware accelerators have been proposed to reduce power consumption and improve the speed of DCNN computing in recent years. These accelera-tors based on application-specific integrated circuits (ASIC) [7,8,9,10,11,12,13,14,15,16,17,18,19] and fieldprogrammable gate array (FPGA) [20,21,22,23,24,25,26] have achieved low latency and high efficiency on CNN computing. Two classic CNN of AlexNet and VGG have been demonstrated the excellent performance earlier, including UNPU [7], DSIP [12], Eyeriss [13], and DNPU [18].…”

Section: Introductionmentioning

confidence: 99%

CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning

Liu

Qiao

Chen

et al. 2022

IEICE Electron. Express

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This work proposes a high-performance reconfigurable CNN accelerator architecture, called CASSANN-v2, which can achieve 1TOPS peak performance at 1 GHz. CASSANN-v2 provides the function of onchip SRAM memory real-time adaptive tuning by parameter configuration to reduce the intermediate output data transmission to further exploit the acceleration performance. The system simulation results show that CASSANN-v2 exhibits excellent performance on VGG-16 and ResNet-18 inference, with a throughput of 1009.54GOPS and 923.24GOPS at 1 GHz, which achieved 98.59% and 90.20% average processing element utilization, respectively. Compared with state-of-the-art accelerator works, CASSANN-v2 improves the resource utilization by 2.02× in

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An Off-Chip Memory Access Optimization for Embedded Deep Learning Systems

Putra,

Hanif,

Shafique

2023

Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing

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A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications

Cited by 5 publications

References 12 publications

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks

CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning

An Off-Chip Memory Access Optimization for Embedded Deep Learning Systems

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