2023
DOI: 10.1587/elex.20.20230385
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A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving -47.05dBc reference spur and -245.9dB FOM in 40nm CMOS technology

Zhichao Zhang,
Wenjie Zheng,
Xinlin Xia
et al.

Abstract: This paper presents a 20.8-23.2GHz integer-N sub-sampling phase-locked loop (SSPLL) with low-reference spur and low-phase noise. A transformer-coupled based voltage controlled oscillator (VCO) is employed and its output is feedback as the input to SSPD in subsampling PLL to reduce the reference spur without requiring extra area and power consumption. In addition, a common source feedback circuit is adopted in the proposed sub-sampling charge pump (SSCP) to reduce current mismatch. The proposed sub-sampling PLL… Show more

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