A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 &lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;$\times$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt; 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC

Yoshioka, Kentaro; Kubota, Hiroshi; Fukushima, Tadashi; Kondo, Satoshi; Ta, Tuan Thanh; Okuni, Hidenori; Watanabe, K.; Hirono, Masatoshi; Ojima, Yoshinari; Kimura, Kozo; Hosoda, Sohichiroh; Ota, Yutaka; Koizumi, Toru; Kawabe, Naoyuki; Ishii, Yusuke; Iwagami, Yoichiro; Yagi, Seitaro; Fujisawa, Isao; Kano, Nobuo; Sugimoto, Tsuneaki; Kurose, Daisuke; Waki, Naoya; Higashi, Y.; Nakamura, Tetsuya; Nagashima, Yoshikazu; Ishii, Hirotomo; Sai, Akihide; Matsumoto, Nobu

doi:10.1109/jssc.2018.2868315

Cited by 63 publications

(28 citation statements)

References 19 publications

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“…Copyright c 2019 The Institute of Electronics, Information and Communication Engineers improve the performance of QBPDSM, the noise coupling (NC) SAR quantizer is used for realizing high order noise shaping and image rejection. The SAR-assisted digital domain noise coupling technique can easily realize the high order noise shaping with maintaining the high energy efficiency, which is verified in pervious works [5]- [7]. In our work, the digital domain noise coupling technique is applied to the implementation of the NC SAR quantizer, moreover, a passive adder is embedded in the NC SAR quantizer to further improve the energy efficiency of the QBPDSM.…”

Section: Introductionsupporting

confidence: 63%

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

Pan

San

2019

IEICE Trans. Fundamentals

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This paper presents a 6th-order quadrature bandpass delta sigma AD modulator (QBPDSM) with 2nd-order image rejection using dynamic amplifier and noise coupling (NC) SAR quantizer embedded by passive adder for the application of wireless communication system. A novel complex integrator using dynamic amplifier is proposed to improve the energy efficiency of the QBPDSM. The NC SAR quantizer can realize an additional 2nd-order noise shaping and 2nd-order image rejection by the digital domain noise coupling technique. As a result, the 6th-order QBPDSM with 2nd-order image rejection is realized by two complex integrators using dynamic amplifier and the NC SAR quantizer. The SPICE simulation results demonstrate the feasibility of the proposed QBPDSM in 90 nm CMOS technology. Simulated SNDR of 76.30 dB is realized while a sinusoid −3.25 dBFS input is sampled at 33.3 MS/s and the bandwidth of 2.083 MHz (OSR=8) is achieved. The total power consumption in the modulator is 6.74 mW while the supply voltage is 1.2 V. key words: quadrature bandpass delta sigma modulator, image rejection, SAR quantizer, noise coupling, ring amplifier, complex integrator

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Section: Introductionsupporting

confidence: 63%

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

Pan

San

2019

IEICE Trans. Fundamentals

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“…KB Vaibhav et al, presented a review article for high speed ADCs with comparison of different architectures with low power CMOS. The article details Flash ADCs, pipelined ADCs, SAR ADCs [28][29][30], subranging and two step ADCs, interpolating and folding ADCs to be suitable for the hybrid ADC design to perform high speed operations with the benefit in power values. The paper also talks about the hybrid ADC for applications demanding 1-GS/s with 6-bits resolution [31].…”

Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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“…High-resolution time-to-digital converters (TDCs) are widely used in medical time-of-flight (TOF) positron emission tomography (PET) cameras [1][2][3], light detection and ranging (LiDAR) [4][5][6], large high-altitude air shower observatory systems (LHAASO) [7][8][9], and high-energy physics (HEP) experiments [10]. Many applications have a requirement for temperature-insensitive high-performance TDCs that will provide stable and reliable operation over a wide range of temperatures.…”

Section: Introductionmentioning

confidence: 99%

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

Song

Zhao

et al. 2020

Sensors

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This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.

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A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 <inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC

Cited by 63 publications

References 19 publications

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer

Analog to Digital Converters (ADC): A Literature Review

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

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