A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

Abstract

A 9.5 mW 20 Gb/s 40 x 70 /_m2 inductorless 1:4 DEMUX in 90 nm CMOS process is presented. In order to reduce power and area, the DEMUX uses a multi-phase clock architecture that requires a smaller number of latches operating at a slower clock rate than in the conventional tree architecture. To provide low-voltage scalability, the latches operate with a near-tail-to-rail logic swing. It is realized without significant speed penalty by adopting current-sourceless CML-type latches with unconventional settings. It offers a larger noise margin and elimination of logic level converters too. The well-balanced scalable design could possibly broaden the applications of high-speed SerDes in the coming ultralowvoltage many-core era.Index Terms -DEMUX, CMOS, multi-phase clock architecture, near-rail-to-rail logic swing I. INTRODUCTION Applications of high-performance demultiplexers (DEMUXes) [1]-[6] have so far been limited chiefly to those that accept a design trade-off in favor of speed, such as fiberoptic communication systems. In typical optical wavelengthdivision multiplexing (WDM) systems, for example, perwavelength speed of 10 Gb/s or faster is required. The conventional wisdom in gaining or maintaining speed of CML-type circuits, used in [1]-[6], has been to reduce the signal amplitude. A dilemma here is that the noise immunity might have to be traded off. Another problem is that current-mode logic (CML)-type circuits do not go well with the trend of lowering the supply voltage. As regards other factors than the speed, since as many DEMUXes as the wavelength multiplicity are needed in WDM systems, the power and area are also important considerations. We present a 1:4 DEMUX with near-rail-to-rail architecture that could offer a possible solution to the challenges in signal integrity and low-voltage scalability as well as in balancing the speed, power, and area.

Design of a Low‐Power 20Gb/s 1:4 Demultiplexer in 0.18μm CMOS

“…So the multi-phase clock 1:4 DEMUX can not only greatly raise work rate, but also reduce power consumption and chip area [6,7] .…”

“…With the development of CMOS technology during these years, the characteristic frequency fT continues to rise. There have been some over 10Gb/s DEMUX in various CMOS technology [4][5][6][7][8] . In those DEMUX designs, the circuit mostly used the Currentmode logic (CML) or improved CML structure, but the CMOS logic which has the advantages of simple structure and low power consumption was seldom used.…”

A low power 12Gb/s 1:4 demultiplexer in 0.18μm CMOS

“…CMOS technology has been demonstrated to be viable for high speed DEMUX with a date rate beyond 10 Gb/s [4]- [7]. In those past published demultiplexer circuits, source coupled FET logic (SCFL) structure is used mostly.…”

Design of a high speed and power efficient quarter-rate clock and data recovery circuit

“…In terms of power efficiency, the proposed DEMUX is in second place. The main reason for [71] to have the best performance in power efficiency is that it is implemented in 90-nm technology. If the proposed DEMUX is implemented in the same technology, it will also have a better performance in power efficiency.…”

“…4[71,72]. The half-rate clock, CLK IN , is first passed through a frequency divider to generate a four-phase quarter-rate clock, CLK I and CLK Q .…”