A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Matsui, M.; Hara, Hiroyuki; Uetani, Yoshiharu; Kim, Lee-Sup; Nagamatsu, T.; Watanabe, Yoshihiro; Chiba, A.; Matsuda, K.; Sakurai, Takayasu

doi:10.1109/4.340421

Cited by 127 publications

(61 citation statements)

References 13 publications

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“…1. A pair of shows a typical circuit of differential sense-amplifier type FF (Diff FF) [1]- [3]. This kind of circuit is extremely effective to amplify small-swing signals, therefore is usually utilized in output of memory circuits.…”

Section: Related Workmentioning

confidence: 99%

Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC

Lakshminarayanan¹,

Jayapal²,

Shankar³

et al. 2014

International Journal of Advanced Research in Computer and Comm

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An extremely low-power flip-flop named topologically-compressed flip-flop is planned. As compared with standard FFs, the FF reduces power dissipation by seventy fifth at 1/3 information activity. This power reduction magnitude relation is that the highest among FFs that are reported thus far. The reduction is achieved by applying topological compression methodology, merger of logically equivalent transistors to associate unconventional latch structure. The terribly little variety of transistors, only three, connected to clock signal reduces the facility drastically, and therefore the smaller total transistor count assures identical cell space as standard FFs. In addition, absolutely static full-swing operation makes the cell tolerant of provide voltage and input slew variation. associate experimental chip design with forty nm CMOS technology shows that nearly all standard FFs are replaceable with planned FF whereas protective the same system performance and layout space.

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Section: Related Workmentioning

confidence: 99%

Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC

Lakshminarayanan¹,

Jayapal²,

Shankar³

et al. 2014

International Journal of Advanced Research in Computer and Comm

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“…A schematic of the sense amplifier (SA) is presented in Fig. 10(b) [16]. The data evaluation time and sensitivity are important performance metrics of the data/edge samplers.…”

Section: A Cdr Building Blocksmentioning

confidence: 99%

A Wide-Tracking Range Clock and Data Recovery Circuit

Hanumolu

Wei

Moon

2008

IEEE J. Solid-State Circuits

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Abstract-A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 m CMOS process achieves BER 10 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than 5000 ppm and 2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.Index Terms-Clock and data recovery, phase-locked loop (PLL), spread-spectrum clocking, digital phase interpolation, delta-sigma.

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“…The computational costs of the H.263 codec is lower than those of the MPEG 1/2 cores. The DCTIIDCT architectures, which have been developed for MPEG112 (Matsui, 1994) (Uramoto, 1992) (Masaki, 1995), should not be employed for H.263 from the view point of hardware cost, and therefore in what follows a novel specific architecture is proposed for H.263. For implementing DCTIIDCT core the Chen's algorithm (Chen, 1977) (butterfly computation) is widely used in conjunction with a distributed arithmetic (Peled, 1974).…”

Section: Dct/idct Corementioning

confidence: 99%

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing

Miki

Fujita

Kobayashi

et al. 1997

VLSI: Integrated Systems on Silicon

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A number of novel VLSI architectures are devised for an H.263 video codec core in terms of low bitrate visual communication. The potential of the practicability for mobile computing has been extremely explored by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15MHz. The whole encoding and decoding facilities have been integrated in the die area of 7.66 mm 2 by means of a 0.35m CMOS technology, with the dissipation of 146.60 mW from a single 3.3V supply.

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A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Cited by 127 publications

References 13 publications

Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC

Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC

A Wide-Tracking Range Clock and Data Recovery Circuit

A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing

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