A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller

Mayes, M.K.; Chin, S.W.

doi:10.1109/4.545806

Cited by 40 publications

(7 citation statements)

References 10 publications

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“…In contrast to single-bit modulators, where can be as large as twice the supply voltage, the maximum step input to the first integrator is generally much smaller in a multibit modulator, and, hence, the operational amplifier response is generally dominated by linear settling. If it is assumed that linear settling to within 0.5 LSB of the asymptotic value is required to avoid distortion that results from incomplete settling, and if the input transistors are assumed to have a square-law response, then, following a derivation similar to that presented in [8], the power dissipation in the first integrator can be approximated by (3) where is the overdrive voltage of the input transistors, is the linearity expressed in number of bits, and is the supply voltage.…”

Section: A Technology Limits On Oversampling Ratiomentioning

confidence: 99%

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A 2.5-V sigma-delta modulator for broadband communications applications

Vleugels¹,

Rabii²,

Wooley³

2001

IEEE J. Solid-State Circuits

129

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Oversampled sigma-delta (61) modulators offer numerous advantages for the realization of high-resolution analogto-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution 61 modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-m double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply.Index Terms-Analog-to-digital conversion, CMOS analog integrated circuits, double sampling, dynamic element matching, integrated circuit design, mixed analog-digital integrated circuits, sampled-data circuits, sigma-delta modulation, switched-capacitor circuits.

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Section: A Technology Limits On Oversampling Ratiomentioning

confidence: 99%

“…Although pipelined A/D converters are generally preferred for realizing high conversion rates, their sensitivity to component mismatch results in a significant increase in complexity and, potentially, power dissipation if resolutions beyond 14 bits are envisioned [2], [3].…”

Section: Introductionmentioning

confidence: 99%

A 2.5-V sigma-delta modulator for broadband communications applications

Vleugels¹,

Rabii²,

Wooley³

2001

IEEE J. Solid-State Circuits

129

View full text Add to dashboard Cite

show abstract

“…The calibration algorithm provides a linear gain estimate, but is not able to correct for stage gain nonlinearity caused by low open-loop gain in the MDAC [12]. Therefore, the operational transconductance amplifiers (OTAs) used in the MDACs employ folded-cascode topologies with gain boosting to ensure high open-loop gain over the operating range of the amplifier [13].…”

Section: Adc Calibrationmentioning

confidence: 99%

ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment

Grace

Braga

Chen

et al. 2022

IEEE Trans. Nucl. Sci.

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The second and final version of ColdADC, called ColdADC_P2, is presented. ColdADC_P2 is a 16-channel, 12-bit, 2 MS/s Digitizer ASIC intended for use inside the DUNE Far Detector. ColdADC_P2 contains two 16 MS/s Pipelined ADCs that each digitizes the output of 8 sample-and-hold amplifiers. Because the application requires immersion in liquid argon, ColdADC_P2 was developed using specialized design techniques for long-term reliability in cryogenic environments and a customized cryogenic standard cell library. ColdADC_P2, with a die area of approximately 52.4 mm 2 and fabricated in 65 nm CMOS technology, achieves 130 µV-rms noise performance and 11.8-bit ENOB at a temperature of 77 K, with channel-to-channel crosstalk of < 0.06% while dissipating 338 mW (21 mW per channel). Residual nonlinearity that is consistent with dielectric absorption in the capacitors internal to the ADC is corrected using a lookup table.

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“…ADCs based on a pipelined architecture have been found to be well-suited to the demands of digital imaging [2]. To enable increased levels of integration and to reduce overall system complexity, readout systems for integrated imagers are typically implemented in CMOS technology [3].…”

Section: Code-density-based Calibrationmentioning

confidence: 99%

Code-density calibration of Nyquist-rate analog-to-digital converters

Grace

Denes

Gnani

et al. 2012

2012 IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC)

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An analog-to-digital converter (ADC) calibration algorithm based on measuring and correcting the code-density histogram of the converter under calibration is presented. The algorithm constructs a histogram of the ADC response to a linear ramp and stores the calculated correction coefficients in a lookuptable. By leveraging circuit density improvements in deep submicron CMOS technology, the algorithm is able to provide substantive improvements to ADC static linearity performance at low silicon cost. The algorithm is applied to a 12-stage prototype Pipelined ADC implemented in 65 nm CMOS technology and is able to improve measured integral nonlinearity from -5.31/1.02 least significant bit (LSB) to -0.24/0.31 LSB at a 10-bit level, an improvement of over three effective bits.

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A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller

Cited by 40 publications

References 10 publications

A 2.5-V sigma-delta modulator for broadband communications applications

A 2.5-V sigma-delta modulator for broadband communications applications

ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment

Code-density calibration of Nyquist-rate analog-to-digital converters

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