Proceedings of 1994 IEEE Symposium on VLSI Circuits
DOI: 10.1109/vlsic.1994.586225
|View full text |Cite
|
Sign up to set email alerts
|

A 200mhz 16mbit Synchronous Dram With Block Access Mode

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
2
0

Publication Types

Select...
5

Relationship

0
5

Authors

Journals

citations
Cited by 9 publications
(2 citation statements)
references
References 2 publications
0
2
0
Order By: Relevance
“…In order to overcome the delay inconsistency, the second stage is split further and an additional latch is inserted into the read data (RD) line as shown in Fig. 1(b) [3]. This results in the reduction of the delay time in the second stage with a loss of signal's S/N ratio and increase of , the CAS latency, from three to four.…”
Section: Comparisons Of Different Pipeline Architecturesmentioning
confidence: 99%
See 1 more Smart Citation
“…In order to overcome the delay inconsistency, the second stage is split further and an additional latch is inserted into the read data (RD) line as shown in Fig. 1(b) [3]. This results in the reduction of the delay time in the second stage with a loss of signal's S/N ratio and increase of , the CAS latency, from three to four.…”
Section: Comparisons Of Different Pipeline Architecturesmentioning
confidence: 99%
“…Different pipeline architectures have been widely employed in the SDRAM for high-speed operation [1], [3]- [8]. However, little discussion on their performances or comparison with each other has been reported.…”
Section: Introductionmentioning
confidence: 99%