A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process

Sangalang, Ralph Gerard B.; Reddy, Shiva; Tolentino, Lean Karlo S.; Shen, Yi; Jose, Oliver Lexter July A.; Wang, Chua‐Chin

doi:10.1109/tcsii.2023.3289911

IEEE Trans. Circuits Syst. II

2023

DOI: 10.1109/tcsii.2023.3289911

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A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process

Ralph Gerard B. Sangalang

Shiva Reddy

Lean Karlo S. Tolentino

et al.

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Low-complexity Dual Voltage Level Circuitry For Voltage-Divider-Based Content-Addressable Memory (CAM) Based On Two Supply Voltages

Caisaluisa,

Holguín,

Prócel

2024

2024 IEEE Eighth Ecuador Technical Chapters Meeting (ETCM)

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Low-complexity Dual Voltage Level Circuitry For Voltage-Divider-Based Content-Addressable Memory (CAM) Based On Two Supply Voltages

Caisaluisa,

Holguín,

Prócel

2024

2024 IEEE Eighth Ecuador Technical Chapters Meeting (ETCM)

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A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process

Cited by 1 publication

References 18 publications

Low-complexity Dual Voltage Level Circuitry For Voltage-Divider-Based Content-Addressable Memory (CAM) Based On Two Supply Voltages

Low-complexity Dual Voltage Level Circuitry For Voltage-Divider-Based Content-Addressable Memory (CAM) Based On Two Supply Voltages

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