A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology

Toifl, Thomas; Menolfi, Christian; Ruegg, Michael; Reutemann, R.; Buchmann, P.; Kossel, Marcel; Morf, Thomas; Weiß, Jonas; Schmatz, M.

doi:10.1109/jssc.2006.870898

Cited by 74 publications

(23 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Several analog front-ends for amplifying and detecting PAM constellations have been reported in the literature [3][4][5]. The front-end of the 22Gb/s PAM-4 CDR from [3] (see Fig.…”

Section: The Proposed Analog Front-endmentioning

confidence: 99%

See 1 more Smart Citation

Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS

Sadeghipour

Townsend

Ossieur

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

We 1 present an analog front end for a PAM-4 clock and data recovery circuit designed in 65nm CMOS. The front end consists of an arrangement of 8 interleaved master and slave sample-and-hold circuits, to be followed by an array of dynamic comparators. Each interleaved channel contains two wideband buffers with accurate bias and common-mode control circuitry to drive the sample-and-hold circuits. The worst-case (across process, temperature and supply voltage corners) aperture time of the sampling front end is 17ps for a differential input voltage swing of 200mV, sufficient to resolve a 56Gb/s (28Gbaud) PAM-4 signal. The power consumption is 55mW from 1.0V and 1.2V supply voltages.

show abstract

“…Several analog front-ends for amplifying and detecting PAM constellations have been reported in the literature [3][4][5]. The front-end of the 22Gb/s PAM-4 CDR from [3] (see Fig.…”

Section: The Proposed Analog Front-endmentioning

confidence: 99%

“…The front-end of the 22Gb/s PAM-4 CDR from [3] (see Fig. 2) used three voltage-shifting amplifiers to generate amplified copies of the input signal, with two copies shifted by an offset +/-V.…”

Section: The Proposed Analog Front-endmentioning

confidence: 99%

Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS

Sadeghipour

Townsend

Ossieur

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…The next modification on the signal path needs to be done after the TIA to properly demodulate the down-converted four-level ASK signal [18,19]. Therefore a slicer, shown in Fig.…”

Section: Extension To Multi-level Askmentioning

confidence: 99%

A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

Tikka

Viitala

Ryynänen

2015

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents a fully integrated 40-GHz transceiver designed for 2 Gbit/s short-range chip-to-chip communication link. The proposed architecture includes both the transmitter and the receiver and is optimized for on-off-keying modulation scheme. The transceiver design includes two variants, which can drive either a planar onchip antenna or wire-bonded off-chip antenna. The performance comparison of these is given in the paper. A compact and energy-efficient technique has been adopted by directly modulating the oscillator in the transmitter. The receiver uses a self-mixing topology followed by transimpedance amplifier and a limiter chain. The detailed circuit descriptions as well as design trade-offs with simulation results in 65 nm CMOS are given. In addition, an example design modification to extend the modulation to 4-level amplitude shift keying is presented.

show abstract

“…[nm] need for a Digital-to-Analog Converter (DAC) at the transmitters, an Analog-to-Digital Converter (ADC) at the receiver, and complex clock recovery schemes [17][18][19][20][21][22][23][24]. High-order PAM was also used for wireline communications to improve spectral efficiency.…”

Section: Referencesmentioning

confidence: 99%

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Yuan¹

2014

J Elec Electron Syst

View full text Add to dashboard Cite

A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology

Cited by 74 publications

References 10 publications

Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS

Design of a sample-and-hold analog front end for a 56Gb/s PAM-4 receiver using 65nm CMOS

A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS

Design Techniques for High-Speed I/Os: Challenges and Opportunities

Contact Info

Product

Resources

About