A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout

Deaville, Peter; Zhang, Bonan; Verma, Naveen

doi:10.1109/vlsitechnologyandcir46769.2022.9830153

Cited by 28 publications

(8 citation statements)

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“…The adoption of resistive memory elements limits possible implementations to NVM technologies only, since SRAM cells cannot provide ohmic behavior or work with analog voltages. NVM-based analog accelerators have been implemented with RRAM [94], [156]- [158], PCM [72], [159]- [161], STT-MRAM [103], [162] and FeFET devices [163].…”

Section: Fully Analog Circuitsmentioning

confidence: 99%

In-Memory Computing for Machine Learning and Deep Learning

Lepri

Glukhov

Cattaneo

et al. 2023

IEEE J. Electron Devices Soc.

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In-memory computing (IMC) aims at executing numerical operations via physical processes, such as current summation and charge collection, thus accelerating common computing tasks including the matrix-vector multiplication. While extremely promising for memory-intensive processing such as machine learning and deep learning, the IMC design and realization must face significant challenges due to device and circuit nonidealities. This work provides an overview of the research trends and options for IMC-based implementations of deep learning accelerators with emerging memory technologies. The device technologies, the computing primitives, and the digital/analog/mixed design approaches are presented. Finally, the major device issues and metrics for IMC are discussed and benchmarked.

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Section: Fully Analog Circuitsmentioning

confidence: 99%

In-Memory Computing for Machine Learning and Deep Learning

Lepri

Glukhov

Cattaneo

et al. 2023

IEEE J. Electron Devices Soc.

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show abstract

“…The effective dynamic range in each CIM array is calculated as the ratio between maximum signal amplitude and worse case error (at a 3σ confidence interval) from the reported statistical measured v/s ideal MAC result plot. Although [12] achieves 128 rows in parallel, the effective dynamic range is only 12dB. Due to the capacitor-based compute, no active current is drawn during compute and VC-MRAM CIM solution achieve 1.5× -30× higher energy efficiency compared to other non-volatile solutions.…”

Section: F Comparison With Other Workmentioning

confidence: 99%

“…The device resistance also suffers from drifting over time. The authors of [12] and [13] proposed CIM macros using STT-MRAM. However, the STT-MRAM's MTJs exhibit low resistances during both ON and OFF states, and a low ON/OFF ratio.…”

Section: Introductionmentioning

confidence: 99%

“…The low ON/OFF ratio severely degrades achievable compute dynamic range in the presence of inevitable device mismatches. Note that the CIM macro in [12] achieves only 4 effective rows 1 . While [13] turns on 64 rows at the same time, achieved dynamic range is far less 2 .…”

Section: Introductionmentioning

confidence: 99%

“…Since stored bits are available as CMOS logic levels, high accuracy CIM such as capacitor based CIM is enabled with high parallelism (> 1000 rows) without degrading the signal 1 As evident from the plot in Fig. 5 of [12]. 2 The statistical plot of the measured vs. ideal MAC result (Fig.…”

Section: Introductionmentioning

confidence: 99%

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