A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications

Li, Zhiqun; Cheng, Guoxiao; Han, Tingting; Tian, Mi

doi:10.1109/tvlsi.2020.3014962

Cited by 10 publications

(10 citation statements)

References 31 publications

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“…The proposed self-biased circuit is shown in Figure 3. N[0], N [1], N [2], N [3], N [4], N [5], N [6], and N [7] are the corresponding bits of the 8-bit programmable frequency divider. The current I 1 is related to I 0 by…”

Section: The Self-biased Circuitmentioning

confidence: 99%

“…The variable resistor is composed of three branches. N7B is the inverse of the N [7]. The transistor size ratio of each branch is 1:6:2. β P , β P = µ P •C ox •W/L, represents the transistor parameters of the smallest size branch, and X represents the relationship between the total size of the transistor of the variable resistor and the smallest size branch.…”

Section: The Lpf With a Variable Resistormentioning

confidence: 99%

“…PLL is a closed-loop feedback system [5][6][7]. The loop bandwidth and damping factor of the PLL will affect the PLL loop characteristics, such as the stability and locking time [8][9][10].…”

Section: Introductionmentioning

confidence: 99%

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A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

Tian

et al. 2021

Electronics

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This article presents a novel self-biased phase-locked loop (PLL) scheme for wireless local area network (WLAN) applications. A novel self-biased circuit that contains a current mirror circuit and a variable resistor circuit related to the frequency division ratio are proposed. The proposed self-biased PLL scheme achieves a fixed damping factor. Moreover, the self-biased technology allows the PLL loop bandwidth to track the input reference frequency and division ratio. The proposed start-up circuit speeds up the locking of the PLL. In addition, the proposed differential-to-single-ended (DTS) converter can guarantee a 50% duty cycle without operating the PLL at twice the chip operating frequency. The proposed self-biased PLL is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The measured root-mean-square jitter (RMS-jitter) integrated of PLL is 2.4 ps with a dissipation of 8.6 mW, and the resulting figure-of-merit is −223.05 dBc/Hz.

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Section: The Self-biased Circuitmentioning

confidence: 99%

Section: The Lpf With a Variable Resistormentioning

confidence: 99%

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A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

Tian

et al. 2021

Electronics

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“…8,9 For the wideband mm-wave frequency synthesizers, Figure 1 shows various implementation architectures. [10][11][12][13] The most commonly used frequency synthesizer based on fundamental VCO (voltage controlled oscillator) is depicted in Figure 1A. 10 However, the phase noise of CMOS (complementary metal oxide semiconductor) fundamental oscillator is usually limited due to the low-quality factor of varactors at mm-wave.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, a feasible scheme is to use a wideband VCO array cascaded with a wideband frequency multiplier to generate an ultra-wideband mm-wave local oscillator (LO) signal, as illustrated in Figure 1C. 12,13 Compared with the other two ways, this scheme has lower phase noise and power consumption. However, it is difficult to design an ultra-wideband frequency multiplier which can meet mm-wave multiband 5G communication systems.…”

Section: Introductionmentioning

confidence: 99%

A 22.7‐ to 44.2‐GHz Darlington dual‐injection injection‐locked frequency tripler with >35dBc harmonic rejection for multiband 5G communication systems

Wang²,

Qian

et al. 2021

Circuit Theory & Apps

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This paper presents an ultra-wideband varactor-less injection-locked frequency tripler (ILFT) based on Darlington dual-injection topology targeting millimeter-wave multiband fifth generation (5G) communication systems. By utilizing the proposed Darlington dual-injection injector, the current injection efficiency is improved; thus, the locking range is extended significantly without introducing the varactors. In addition, the Darlington dual-injection topology enhances the harmonic rejection performance by suppressing undesired harmonics. Implemented in 65-nm CMOS (Complementary Metal Oxide Semiconductor) technology, the proposed ILFT can operate from 22.7 to 44.2 GHz and consumes 6.2 mA at 1.2 V supply voltage. The harmonics rejection is more than 35 dBc and occupies 0.17 mm 2 .

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Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor

Yang,

Chen,

Cheng

et al. 2024

Circuit Theory & Apps

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In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real‐world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra‐wide‐tuning‐range complementary metal–oxide–semiconductor (CMOS) voltage‐controlled oscillators (VCOs) that employ a novel two‐mode current‐starved delay cell, featuring a tunable transistor‐based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65‐nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter‐based counterpart (Design 1). Design 1 featured an inverter‐based four‐phase structure, with an output frequency range of 3.14–9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14–9.17, 1.26–16.53, and 1.15–18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1–138, 130.5–131.3, and 131.9–129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2–209.9, 205.3–217.9, and 194.1–209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm2 in the same 65 nm technology. These designs showcase the versatility and efficiency of the two‐mode current‐starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits.

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A 23–36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications

Cited by 10 publications

References 31 publications

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

A Novel Self-Biased Phase-Locked Loop Scheme for WLAN Applications

A 22.7‐ to 44.2‐GHz Darlington dual‐injection injection‐locked frequency tripler with >35dBc harmonic rejection for multiband 5G communication systems

Area‐efficient ultra‐wide‐tuning‐range ring oscillators in 65‐nm complementary metal–oxide–semiconductor

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