A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication

Saeedi, Saeed; Menezo, Sylvie; Parès, G.; Emami, Azita

doi:10.1109/jlt.2015.2494060

Cited by 66 publications

(40 citation statements)

References 7 publications

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“…To understand the energies involved in receiver circuits, consider, for example, a recent low-energy photodiode and receiver design [112]. The photodiode has ~ 8fF or less capacitance and the hybrid (solder-bump) packaging technique adds about another 25 fF for a total capacitance of ~ 30fF.…”

Section: A Receiver Circuit Energiesmentioning

confidence: 99%

“…This example gives a receiver circuit operating at 170 fJ/bit at 25 Gb/s with -14.9 dBm noise-limited sensitivity. Such a receiver circuit energy per bit is impressively low; other circuits (see [112] for comparisons) can dissipate as much as several pJ/bit.…”

Section: A Receiver Circuit Energiesmentioning

confidence: 99%

“…In the work of [112], including the input coupling loss of ~ 6 dB, the effective responsivity of the photodetector is 0.2 A/W. -14.9 dBm is equivalent to a power of 32.3 μW, so at 25 Gb/s the photodetector is receiving an optical energy of ~ 1.3 fJ/bit, which will be generating ~ 260 aC/bit of charge in the photodetector.…”

Section: A Receiver Circuit Energiesmentioning

confidence: 99%

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Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Miller

2017

J. Lightwave Technol.

605

406

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Optics offers unique opportunities for reducing energy in information processing and communications while simultaneously resolving the problem of interconnect bandwidth density inside machines. Such energy dissipation overall is now at environmentally significant levels; the source of that dissipation is progressively shifting from logic operations to interconnect energies. Without the prospect of substantial reduction in energy per bit communicated, we cannot continue the exponential growth of our use of information. The physics of optics and optoelectronics fundamentally addresses both interconnect energy and bandwidth density, and optics may be the only scalable solution to such problems. Here we summarize the corresponding background, status, opportunities, and research directions for optoelectronic technology and novel optics, including sub-femtojoule devices in waveguide and novel 2D array optical systems. We compare different approaches to low-energy optoelectronic output devices and their scaling, including lasers, modulators and LEDs, optical confinement approaches (such as resonators) to enhance effects, and the benefits of different material choices, including 2D materials and other quantum-confined structures. With such optoelectronic energy reductions, and the elimination of line charging dissipation by the use optical connections, the next major interconnect dissipations are in the electronic circuits for receiver amplifiers, timing recovery and multiplexing. We show we can address these through the integration of photodetectors to reduce or eliminate receiver circuit energies, free-space optics to eliminate the need for timing and multiplexing circuits (while also solving bandwidth density problems), and using optics generally to save power by running large synchronous systems. One target concept is interconnects from ~ 1 cm to ~ 10 m that have the same energy (~ 10fJ/bit) and simplicity as local electrical wires on chip.

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Section: A Receiver Circuit Energiesmentioning

confidence: 99%

Section: A Receiver Circuit Energiesmentioning

confidence: 99%

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Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Miller

2017

J. Lightwave Technol.

605

406

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“…Transimpedance amplifiers designed for optical interconnects operate at the ∼ 100 fJ range [59,26], while ADCs in the few-pJ/sample regime are available [60] and simple arithmetic (for the activation function) can be performed at the pJ scale [15,16,17]. Modulators in this energy range are standard [56,57,59]. Thus a reasonable near-term estimate would be few-pJ/neuron; this figure is divided by the number of inputs per neuron to give the energy per MAC (solid green curve in Fig.…”

Section: Energy Budgetmentioning

confidence: 99%

Large-Scale Optical Neural Networks Based on Photoelectric Multiplication

Hamerly¹,

Bernstein²,

Sludds³

et al. 2019

Phys. Rev. X

313

243

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Recent success in deep neural networks has generated strong interest in hardware accelerators to improve speed and energy consumption. This paper presents a new type of photonic accelerator based on coherent detection that is scalable to large (N 10 6 ) networks and can be operated at high (GHz) speeds and very low (sub-aJ) energies per multiply-and-accumulate (MAC), using the massive spatial multiplexing enabled by standard free-space optical components. In contrast to previous approaches, both weights and inputs are optically encoded so that the network can be reprogrammed and trained on the fly. Simulations of the network using models for digit-and image-classification reveal a "standard quantum limit" for optical neural networks, set by photodetector shot noise. This bound, which can be as low as 50 zJ/MAC, suggests performance below the thermodynamic (Landauer) limit for digital irreversible computation is theoretically possible in this device. The proposed accelerator can implement both fully-connected and convolutional networks. We also present a scheme for back-propagation and training that can be performed in the same hardware. This architecture will enable a new class of ultra-low-energy processors for deep learning.In recent years, deep neural networks have tackled a wide range of problems including image analysis [1], natural language processing [2], game playing [3], physical chemistry [4], and medicine [5]. This is not a new field, however. The theoretical tools underpinning deep learning have been around for several decades [6,7,8]; the recent resurgence is driven primarily by (1) the availability of large training datasets [9], and (2) substantial growth in computing power [10] and the ability to train networks on GPUs [11]. Moving to more complex problems and higher network accuracies requires larger and deeper neural networks, which in turn require even more computing power [12]. This motivates the development of special-purpose hardware optimized to perform neural-network inference and training [13].To outperform a GPU, a neural-network accelerator must significantly lower the energy consumption, since the performance of modern microprocessors is limited by on-chip power [14]. In addition, the system must be fast, programmable, scalable to many neurons, compact, and ideally compatible with training as well as inference. Application-specific integrated circuits (ASICs) are one obvious candidate for this task. Stateof-the-art ASICs can reduce the energy per multiply-and-accumulate (MAC) from 20 pJ/MAC for modern GPUs [15] to around 1 pJ/MAC [16,17]. However, ASICs are based on CMOS technology and therefore suffer from the interconnect problem-even in highly optimized architectures where data is stored in register files close to the logic units, a majority of the energy consumption comes from data movement, not logic [13,16]. Analog crossbar arrays based on CMOS gates [18] or memristors [19,20] promise better performance, but as analog electronic devices, they suffer from calibration issues and li...

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“…SOI wafers with a 0.22 µm silicon guiding layer and 2 µm BOX is the pseudo standard used for SOI-based silicon photonics. However recently thicker silicon layers of 0.31 µm [25] and 0.4 µm [26] are also getting prominence due to the ease of heterogeneous III-V laser integration on these waveguide circuits. The high index contrast of about 2 between the guiding silicon layer (n∼3.5) and the BOX (n∼1.45) allows for a tight bending radius of 5 µm (for 0.45 µm wide strip waveguides operating at 1.55 µm).…”

Section: Silicon Photonics Platformsmentioning

confidence: 99%

Expanding the Silicon Photonics Portfolio With Silicon Nitride Photonic Integrated Circuits

Rahim

Ryckeboer

Subramanian

et al. 2017

J. Lightwave Technol.

276

158

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Abstract-The high index contrast silicon-on-insulator platform is the dominant CMOS 1 compatible platform for photonic integration. The successful use of silicon photonic chips in optical communication applications has now paved the way for new areas where photonic chips can be applied. It is already emerging as a competing technology for sensing and spectroscopic applications. This increasing range of applications for silicon photonics instigates an interest in exploring new materials, as silicon-oninsulator has some drawbacks for these emerging applications, e.g. silicon is not transparent in the visible wavelength range. Silicon nitride is an alternate material platform. It has moderately high index contrast, and like silicon-on-insulator, it uses CMOS processes to manufacture photonic integrated circuits. In this paper, the advantages and challenges associated with these two material platforms are discussed. The case of dispersive spectrometers, which are widely used in various silicon photonic applications, is presented for these two material platforms.

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A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication

Cited by 66 publications

References 7 publications

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Large-Scale Optical Neural Networks Based on Photoelectric Multiplication

Expanding the Silicon Photonics Portfolio With Silicon Nitride Photonic Integrated Circuits

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