A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS

Iwata, Kazunori; Mochizuki, Seibu; Kimura, Masao; Shibayama, Tomoya; Izuhara, Fumitaka; Ueda, Hiroshi; Hosogi, Koji; Nakata, Hiroyuki; Ehama, Masakazu; Kengaku, T.; Nakazawa, T.; Watanabe, Hiromi

doi:10.1109/jssc.2009.2014025

Cited by 25 publications

(16 citation statements)

References 7 publications

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“…For these applications, many work (e.g. [15] and references therein) aim to implement high speed HW H.264 video encoders. Due to the long coding path, H.264 encoders are mostly designed as pipeline architectures, implementing slight modifications in the entire pipeline or in some particular modules to overcome data dependency.…”

Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

“…To solve data dependency among MBs, the parallel pipelines architecture [15] or the modified motion vector prediction in the interprediction block [8] might be applied. Actually, the parallel pipelines architecture enables MBs to be processed in order so that all required information form neighboring MBs is available when the current MB is encoded.…”

Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

“…Some of them are even able to process HDTV1080 30 fps video for real-time application [6,15]. Meanwhile, design focusing on low-power consumption has been raised as a great challenge.…”

Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

“…Others used specific low-power techniques, e.g. power gating and clock gating [9,15,16]. Moreover, the encoder might be reconfigurable to change its profile/features so as to adapt with the power consumption requirements [9,17].…”

Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

“…A high speed codec in high profile is proposed in [15]. It makes use of a two-stage pipeline encoder at frame level.…”

Section: Scalability Andmentioning

confidence: 99%

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An Overview of H.264 Hardware Encoder Architectures Including Low-Power Features

Nguyen

Bui²,

Dang³

et al. 2014

REV-JEC

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Abstract-H.264 is the most popular video coding standard with high potent coding performance. For its efficiency, the H.264 is expected to encode real-time and/or high-definition video. However, the H.264 standard also requires highly complex and long lasting computation. To overcome these difficulties, many efforts have been deployed to increase encoding speed. Besides, with the revolution of portable devices, multimedia chips for mobile environments are more and more developed. Thus, power-oriented design for H.264 video encoders is currently a tremendous challenge. This paper discusses these trends and presents an overview of the state of the art on power features for different H.264 hardware encoding architectures. We also propose the VENGME's design, a particular hardware architecture of H.264 encoder that enables applying low-power techniques and developing power-aware ability. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at Register-TransferLevel (RTL), is only 19.1 mW.

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Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

“…Some of them are even able to process HDTV1080 30 fps video for real-time application [6,15]. Meanwhile, design focusing on low-power consumption has been raised as a great challenge.…”

Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

Section: Trends To Implement Hardware H264 Encodermentioning

confidence: 99%

“…A high speed codec in high profile is proposed in [15]. It makes use of a two-stage pipeline encoder at frame level.…”

Section: Scalability Andmentioning

confidence: 99%

See 3 more Smart Citations