A 25Gb/s RX front-end with multi-stage linear equalizer and 3-tap speculative DFE in 65nm CMOS technology

Abstract

This work proposes a RX front-end structure, which is used for channel equalization of 25 Gb/s high-speed links. This design includes two parts, linear equalizer and decision feedback equalizer. Linear equalizer consists of the variable gain amplifier, the continuous-time linear equalizer and the output buffer, which provide 19 dB peaking gain around the Nyquist frequency. The half-rate decision feedback equalizer with one speculative tap is cascaded after the buffer to eliminate residual inter-symbol interference. The circuit layout occupies an area of 0.005 mm 2 designed in 65 nm CMOS, the power consumption of which is 96 mW under 1.2 V power supply. The design is used to equalize the FR-4 backplane channel, of which the insertion loss reaches 35 dB at 12.5 GHz. The result shows that both the voltage margin and time margin of the receiver signal reach 171 mV and 0.61 UI at the BER of 10 −12 , respectively.

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

“…The data-traffic explosion driven by cloud computing, 5G networks, industrial IoT, and virtual reality has accelerated the demand for high-speed SerDes transceivers to provide massive data throughput [1,2,3,4,5,6,7,8]. Previous studies have demonstrated that four-level pulse amplitude modulation (PAM-4) is superior to non-return-to-zero (NRZ) for the 56∼112-Gb/s serial data communications due to its doubled spectral efficiency, halved Nyquist frequency, and relaxed clock speeds [9,10,11,12,13,14,15].…”