A 26.1–38.2 GHz injection-locked frequency divider with current phasor synthesis technique

Li, Zhen; Zhang, Yiqi; Li, Zhenrong; Qian, Xing; Wang, Zeyuan

doi:10.1016/j.aeue.2020.153105

Cited by 5 publications

(3 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The transformer should be carefully designed and occupy a large die area due to the low coupling factor. A current phasor synthesis technique is proposed 20 to increase the LR of the mm‐wave ILFD, and the forward body bias technique is utilized to reduce supply voltage. However, using the R‐C poly phase filter added more noise to the circuit, causing the phase noise of the frequency divider to be reduced.…”

Section: Introductionmentioning

confidence: 99%

Using tail current phase shift technique to improve locking range injection‐locked frequency divider

Ghonoodi

Modanlou

Hadjmohammadi

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryIn this article, an injection‐locked frequency divider (ILFD) is presented. By assuming the maximum phase of the tank current, we obtain a relation for the lock range. Besides, the effects of parasitic capacitors on the lock range have been probed. The analysis shows that the greater the phase difference between the tail current and injected signal, the phase of the tank current increases and, consequently, the lock range also increases. The accomplished simulations confirm the correct performance of the proposed design and the extracted relationships. The simulations have been CMOS technology and with a 0.9‐V supply voltage. The results show that the current consumption equals 3.7 mA and the power consumption equals 3.33 mW. The proposed ILFD lock range with phase shift technique with power input signal 0 dBm is equal to 5.1 GHz (3.6–8.7 GHz), and the relative percentage of the lock range is also 83%.

show abstract

Section: Introductionmentioning

confidence: 99%

Using tail current phase shift technique to improve locking range injection‐locked frequency divider

Ghonoodi

Modanlou

Hadjmohammadi

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Nevertheless, the traditional injection-locked divider has a narrow operation bandwidth. Much research [18,19,20,21,22,23,24,25,26,27,28] has been conducted to enhance the LR of the injection-locked frequency dividers and multipliers. [18] reduces the Q value of the tank to attain a flat phase response.…”

Section: Introductionmentioning

confidence: 99%

“…[19] proposes the frequency-tracking technique achieving 39% fractional bandwidth. [20] using the current-synthesis technique realizes a LR from 26.1 GHz to 38.2 GHz. In [23], the design employing the transformer-based high-order resonator exhibits a LR from 32.4 to 61.9 GHz.…”

Section: Introductionmentioning

confidence: 99%

An ultra-wideband injection-locked frequency divider with a multi-order resonator and the passive injection-boosted technique

Cheng

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents an ultra-wideband injection-locked frequency divider (ILFD) design which is applicable to a multi-applications system. A transformer-based multi-order resonator is utilized in the ILFD to attain a flat phase response. The passive injection-boosted technique is proposed to increase the injection signal amplitude and thus widen the locking range. With the injection-boosted technique and the multi-order resonator, the proposed ILFD demonstrates a measured locking range of 50 GHz, covering 48 GHz to 98 GHz. The divider designed in a 40-nm process consumes a DC power of 11.2 mW excluding buffers and occupies a core size of 0.38 × 0.63 mm 2 .

show abstract

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

Effendrik,

Chen

2024

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FMerror/BWchirp and RMS-FMerror/(BWchirp × fc × Tc) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.

show abstract

A 26.1–38.2 GHz injection-locked frequency divider with current phasor synthesis technique

Cited by 5 publications

References 16 publications

Using tail current phase shift technique to improve locking range injection‐locked frequency divider

Using tail current phase shift technique to improve locking range injection‐locked frequency divider

An ultra-wideband injection-locked frequency divider with a multi-order resonator and the passive injection-boosted technique

An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications

Contact Info

Product

Resources

About