A 26.9 K 314.5 Mb/s Soft (32400,32208) BCH Decoder Chip for DVB-S2 System

Abstract

Abstract-This paper provides a soft Bose-Chaudhuri-Hochquenghem (BCH) decoder chip with soft information from the LDPC decoder for the DVB-S2 system. In contrast with the hard BCH decoder, the proposed soft BCH decoder that deals with least reliable bits can provide much lower complexity with similar error-correcting performance. Moreover, the error locator evaluator is proposed to evaluate error locations without the Chien search for higher throughput, and the Björck-Pereyra error magnitude solver (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The chip measurement results reveal that our proposed soft (32400, 32208) BCH decoder for DVB-S2 system can achieve 314.5 Mb/s with a gate-count of 26.9 K in standard 90 nm 1P9M CMOS technology. Extended for fully supporting 21 modes in the DVB-S2 system, our approach can achieve 300 MHz operation frequency with a gate-count of 32.4 K.

Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation

“…For long-block-length BCH decoders, the decoding latency is dominated by the syndrome calculator and the Chien search. Unlike the conventional algorithms using parallel Chien search to enhance throughput, an error-locator evaluator is proposed to eliminate Chien search procedure for higher throughput [10].…”

Improved synchronization, channel estimation, and simplified LDPC decoding for the physical layer of the DVB-T2 receiver

“…The bit processing chain structure is illustrated in Figure 16. The implementation of the bit chain receiver involves a state-of-the-art loglikelihood soft demapper, and BCH decoding [14][15][16]. On the other hand, the LDPC decoder poses a particular implementation challenge regarding the algorithmic and implementation complexity, not to mention its memory requirements.…”

LDPC Error Floor Improvement

“…(3), the conventional BCH decoding contains three major steps. The received polynomial R(x) is loaded into the First In First Out (FIFO) and fed into the syndrome calculator to generate syndrome polynomial [16]. S(x) = S 1 +S 2 x 1 +--------+S 2t x 2t-1 …..(9) which is expressed as :…”

“…Notice that ei is the ith actual error location and β ei indicates the corresponding error locator. The key equation solver is used to carry out the error location polynomial σ(x), which is defined as: [16]…”

“…If an error is occurred at the e i th position, α -ei will be a root of σ(x). Finally, the estimated codeword ( )polynomial is obtained by outputting R(x) from the FIFO and inversing those values at error locations [16].…”