A 27MHz 11.1mW MPEG-4 video decoder LSI for mobile application

Ohashi, Masahiro; Hashimoto, Takashi; Kuromaru, Shun-ichi; Mori-iwa, T.; Hamada, M.; Sugisawa, Yuji; Arita, M.; Tomita, Hironori; Hoshino, Masayuki; Matsubara, Hiroshi; Ishida, K.; Tomoo, Kimura; Kohashi, Y.; Inoue, Akihiko; Fujimoto, Hitoshi; Watada, K.; Nishi, Takahiro; Ito, Hiroyuki; Michiyama, Junji

doi:10.1109/isscc.2002.992261

Cited by 5 publications

(5 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Advances in MPEG4 video standard development has resulted in complex SoCs which features a high logic density and a large number of pins. They consist of many dedicated hardware processing cores [1][2][3] such as a Discrete Cosine Transform (DCT), Inverse DCT (IDCT), Variable Length Coding (VLC), Quantizer (Q), inverse-Quantizer (IQ), Motion Compensator (MC) and Motion Estimator (ME) etc., which possess many different functions. Although large numbers of pins are required, the designer still has very limited access to each processing core inside the SoC.…”

Section: Introductionmentioning

confidence: 99%

Untitled

2009

ijeei

View full text Add to dashboard Cite

This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PCbased interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method.

show abstract

Section: Introductionmentioning

confidence: 99%

Untitled

2009

ijeei

View full text Add to dashboard Cite

show abstract

“…Advances in MPEG4 video standard development has resulted in complex SoCs that feature a high logic density and a large number of pins. They consist of many dedicated hardware processing cores [1,2,3] such as a Discrete Cosine Transform (DCT), Inverse DCT (IDCT), Variable Length Coding (VLC), Quantizer (Q), inverse-Quantizer (IQ), Motion Compensator (MC) and Motion Estimator (ME) etc., which possess many different functions. Although large numbers of pins are required, the designer still has very limited access to each processing core inside the SoC.…”

Section: Introductionmentioning

confidence: 99%

“…DCT module ISET_ADD(0;5,1,0;4,2,0) //Set Frame No=0, Macro-block=5,4 and Block number(1,2) IRD_LINE(0,0,7;0,0,7) // Read a block of data from FSM IWAIT(72) // Wait for 72 clocks ISET_ADD(1;5,1,0;4,2,0) //Set Frame No=1, Macro-block=5,4 and Block number(1,2) IWR_LINE(0;5,1,0;4,2,0) // Write transformed data to FSM ISET_MOD(00h) // Release DCT module ISTOP // Stop the executionThe above program performs the DCT operation to a block of data in frame 0, macro-block (5, 4) and block number(1,2). The result of processing is stored in frame 1, macro-block (5, 4) and block number (1, 2).…”

mentioning

confidence: 99%

An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification

Adiono¹,

Kerkhoff²,

Kunieda³

2009

itbj.ict.

View full text Add to dashboard Cite

This paper introduces a specific architecture including an infrastructural IP for functional verification and diagnostics, which is suitable for functional core-based testing of an MPEG4 SoC. Our advanced MPEG4 SoC results in a high complexity SoC with limited physical access to many different functional cores. The proposed test method provides direct monitoring and control for each core, which enables core verification at actual speed. It significantly decreases the verification time due to the large number of required test vectors in typical MPEG4 verification. Furthermore, it also makes the system scalable for functional core expansion due to upgrading of standards. The proposed infrastructural IP is also linked to PC-based interactive tools to simplify the verification of individual and integrated cores. It also provides detailed diagnostic data that enables simple system debugging. The debugging tools also feature test-pattern generation and simulation of expected values. Actual system implementation has shown full functionality of our proposed method

show abstract

“…

…”

mentioning

confidence: 99%

“…Unlike the realtime decoding of MPEG-4 video [1,4], the performances of hardware-accelerated 3D solutions designed for mobile platforms are still below the market demands showing only limited shading operations [2,3]. Since the realization of various 3D functions requires huge computing power and corresponding memory bandwidth, previous LSIs integrate DRAM using the embedded memory logic technology although it is cost-inefficient due to process complexity.…”

mentioning

confidence: 99%

A 210-mW Graphics LSI Implementing Full 3-D Pipeline With 264 Mtexels/s Texturing for Mobile Multimedia Applications

Woo

Choi

Sohn

et al. 2004

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

As mobile applications are moving to realtime multimedia, more functions are integrated into handheld devices [1][2][3][4]. Unlike the realtime decoding of MPEG-4 video [1,4], the performances of hardware-accelerated 3D solutions designed for mobile platforms are still below the market demands showing only limited shading operations [2,3]. Since the realization of various 3D functions requires huge computing power and corresponding memory bandwidth, previous LSIs integrate DRAM using the embedded memory logic technology although it is cost-inefficient due to process complexity. In this work, a graphics LSI using the pure DRAM technology is implemented to integrate both the logic and memory at low cost. Its circuits and architecture are optimized so that the full 3D pipeline is realized with less than 210mW at the drawing speed of 264Mtexels/s bilinear MIPMAP texturing and antialiasing, applicable to handheld devices.As shown in Fig. 2.4.1, the graphics LSI consists of a 32b RISC, 3D rendering engine (3DRE), 29Mb DRAM, bandwidth equalizer (BEQ) and programmable power optimizer (PPO). The ARM-9 compatible RISC with 4kB I/D caches operates to 132MHz [6]. The RISC includes a 32 x 32b MAC in its datapath to accelerate the 3D geometry operations so that it can calculate as many as 1.04Mvertices/s transformation running a customized fixed-point graphics library, a 43% improvement over the conventional ARM9 processor [5]. SlimShader performs the main rendering operations such as texturing, shading, blending, and depth comparison. Memory Programmer (MP) enables the special effects such as antialiasing, motion blur and fog to be programmable. Integrated 29Mb DRAM with partial wordline scheme [1-3] provides sufficient bandwidth and capacity required for 3D rendering operations. Dedicated hardware engines and 1.6GB/s bandwidth through 416b-wide DRAM lowers the operation frequency of 3DRE even to 33MHz. To compensate the difference of the processing speed and data width between the RISC and 3DRE, BEQ buffers the vertex data with 1kB Dual-Ported SRAM (DP-SRAM). BEQ partially activates the banks of DP-SRAM according to the required buffer size saving 20% power of DP-SRAM. For DSP applications, DP-SRAM can also be used by the RISC as a scratchpad RAM. PPO reduces the power consumption of the chip by varying four different clock domains. 3DRE is shown in Fig. 2.4.2. The triangle setup engine (TSE), which contains single-cycle parallel dividers, distributes polygons to 2 pixel processors (PP). It enhances the overall performance of 3D pipeline by accelerating setup operations which took ~7,000 RISC cycles in the previous work [1][2][3]. A depth-first clock-gating (DFCG) scheme is applied to SlimShader for low power. DFCG can prevent the unnecessary shading and texturing by gating off the clock in the following datapath according to the results of the depth comparison. For realtime special effects, MP post-processes the rendered pixels of the previous frame transferring them to the display controller, while SlimShader renders the ...

show abstract

A 27MHz 11.1mW MPEG-4 video decoder LSI for mobile application

Cited by 5 publications

References 2 publications

Untitled

Untitled

An Infrastructural IP for Interactive MPEG-4 SoC Functional Verification

A 210-mW Graphics LSI Implementing Full 3-D Pipeline With 264 Mtexels/s Texturing for Mobile Multimedia Applications

Contact Info

Product

Resources

About