A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Miyaoka, Hiroki; Terasawa, Futoshi; Kudo, Masahiro; Kano, H.; Matsuda, Atsushi; Shirai, Noriaki; Kawai, S.; Shibasaki, Takayuki; Danjo, Takumi; Ogata, Yudai; Sakai, Yoshihiro; Yamaguchi, Hisakatsu; Mori, Toshihiko; Koyanagi, Yoichi; Tamura, Hirotaka; Ide, Yutaka; Terashima, Kazuhiro; Higashi, Hirohito; Higuchi, Toshiharu; Naka, Naoaki

doi:10.1109/vlsic.2016.7573472

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) 2016

DOI: 10.1109/vlsic.2016.7573472

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A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Hiroki Miyaoka

Futoshi Terasawa

Masahiro Kudo

et al.

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A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

Cited by 1 publication

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