A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

Miyaoka, Hiroki; Terasawa, Futoshi; Kudo, Masahiro; Kano, H.; Matsuda, Atsushi; Shirai, Noriaki; Kawai, S.; Arai, Tomomi; Ide, Yutaka; Terashima, Kazuhiro; Higashi, Hirohito; Higuchi, Toshiharu; Naka, Naoaki

doi:10.1109/asscc.2015.7387468

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A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS

Cited by 2 publications

References 4 publications

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

Per-DFE Offset Measurement and Cancellation of Weighted-VREF-Based Loop-Unrolled DFE for Memory Interfaces

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