A 28 GHz high efficiency fully integrated 0.18 µm combined CMOS power amplifier using power divider technique for 5G millimeter-wave applications

Abstract

A 28 GHz power amplifier (PA) using CMOS 0.18 µm Silterra process technology for milimeter wave applications is reported. Maximizing the power added efficiency (PAE) and output power are achieved by optimize the circuit with power divider and cascade configuration. In addition, reverse body bias is also employed for realizing excellent PAE and power consumption. A three stage CMOS PA with power combiner is designed and simulated. The simulation results show that the proposed PA consumes 62.56 mW and power gain (S21) of 8.08 dB is achieved at 28 GHz. The PA achieves saturated power (Psat) of 12.62 dBm and maximum PAE of 23.74% with output 1-dB compression point (OP1dB) 10.85 dBm. These results demonstrate the proposed power amplifier architecture is suitable for 5G applications.

A 5G mm-wave compact voltage-controlled oscillator in 0.25 µm pHEMT technology

“…The phase noise simulation, presented in Figure 6, shows that phase noise are -96.274 dBc/Hz and -116.27 dBc/Hz at offset frequency 1 MHz and 10 MHz from the carrier, respectively. Nowdays, the energy consumption is an important consideration for wireless communication systems such as 5G [24]. The DC simulation indicates that the power consumption of our VCO circuit is very low, with a power of 111 mW maximum.…”