A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With −101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction

Bolatkale, Muhammed; Rutten, R. J.; Brekelmans, Hans; Bajoria, Shagun; Gao, Yihan; Burdiek, B.; Breems, Lucien J.

doi:10.1109/jssc.2022.3202977

Cited by 7 publications

(1 citation statement)

References 21 publications

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“…Historically, most ADC architectures have been implemented in DT circuits, and CT implementation has been applied almost exclusively to ADCs. Within these classifications, CT ADCs have been the favored choice for fully integrated wireless receiver applications due to their inherent anti-aliasing and resistive input interface [1], [2], [3], [4], [5], [6], [7], [8]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion

Shibata

2023

IEEE Open J. Solid-State Circuits Soc.

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The continuous-time (CT) pipelined analog-to-digital converter (ADC) is an emerging ADC architecture suitable for wide-bandwidth (BW) digitization in fully integrated receiver applications. It inherits the integration-friendly features of CT ADCs, such as inherent anti-aliasing, while achieving the wide-BW operation originating from discrete-time (DT) pipelined ADCs. In this review article, we introduce a gain-centric ADC model and apply the key criteria derived from the model to transform a DT pipelined ADC into a CT pipelined ADC. We then discuss the design considerations and essential building blocks of the CT pipelined ADC. Finally, we examine several implementations of this architecture with their highlights and challenges.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT) ADC, oversampling ADC, pipelined ADC, wideband ADC.

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