A 28nm 6GHz 2b Continuous-Time $\Delta\Sigma$ ADC with −101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction

Bolatkale, Muhammed; Rutten, R. J.; Brekelmans, Hans; Bajoria, Shagun; Gao, Yihan; Burdiek, B.; Breems, Lucien J.

doi:10.1109/isscc42614.2022.9731602

Cited by 4 publications

(3 citation statements)

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“…Also, thanks to the oversampling and low-resolution quantization, static and dynamic calibration as well as dynamic element matching techniques can be effectively employed to achieve very high linearity. This has been demonstrated in many excellent audio ADC designs [1]- [2] and recently <-100 THD has been shown feasible in CT ADCs with bandwidths exceeding 100MHz [3]. If the quantization errors are sufficiently randomized by the delta-sigma modulator (with optional dithering), exceptionally good spurious performance can be realized.…”

Section: Introductionmentioning

confidence: 92%

“…This includes employing reduced switching rate dynamic weighted averaging (DWA) and low ripple DFF designs, achieving a THD of -104dBc at a frequency of 2.2MHz [13]. On the other hand, reference-side switching resistive DACs achieve significantly better THD over wide frequency ranges since their output impedance is independent of the input data [3]. However, for signal BW larger than 120MHz, current steering DACs are preferred.…”

Section: Dac Bits Complexity Linearization Techniques (Static Errors)mentioning

confidence: 99%

“…Consequently, the inherent linearity of the DAC is lost, and it will be sensitive to mismatch. The DAC elements are measured and calibrated with a digital error estimation and correction (DEEC) circuit [3]. The calibration convergence time is less than 1ms.…”

Section: B a 120mhz Bw Ct  Adc With -101db Thdmentioning

confidence: 99%

See 2 more Smart Citations

High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers

Breems,

Bolatkale,

Liu

et al. 2023

IEEE Open J. Solid-State Circuits Soc.

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This paper presents an overview of high-speed and high-performance continuous-time ADCs with a special attention to the application field of automotive receivers for broadcast radio and radar. An overview of the continuous-time ADC architectural space is presented and the key design challenges related to high linearity and broadband signal conversion are described. Insights are given in the architectural and design choices to accomplish high-end performance points. A selection of case studies is presented that achieve state-of-the-art performance metrics with respect to linearity, bandwidth and power efficiency.

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Section: Introductionmentioning

confidence: 92%

Section: Dac Bits Complexity Linearization Techniques (Static Errors)mentioning

confidence: 99%