A 3.1 to 10.6 GHz 100 Mb/s Pulse-Based Ultra-Wideband Radio Receiver Chipset

Lee, F.S.; Blazquez, R.; Ginsburg, Brian; Powell, Johnna; Scharfstein, M.; Wentzloff, David D.; Chandrakasan, Anantha P.

doi:10.1109/icu.2006.281537

Cited by 9 publications

(3 citation statements)

References 12 publications

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“…It is clear that the proposed receiver achieves energy-efficient communication and compares favorable to other implementations. Furthermore results from a true wireless link are shown exceeding previously published results [23], [24].…”

Section: Full Front-end Measurementscontrasting

confidence: 58%

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

Helleputte

Gielen

2009

IEEE J. Solid-State Circuits

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This paper presents an integrated ultra-low power analog front-end (AFE) architecture for UWB impulse radio receivers. The receiver is targeted towards applications like wireless sensor networks typically requiring ultra energy-efficient, low data-rate communication over a relative short range. The proposed receiver implements pulse correlation in the analog domain to severely relax the power consumption of the ADCs and digital backend. Furthermore a fully integrated prototype of the analog front-end, containing a PLL, programmable clocking generator, analog pulse correlator, a linear-in-dB variable gain amplifier and a 4-bit ADC, is demonstrated. Several design decisions and techniques, like correlation with a windowed LO instead of with a matched template, exploiting the duty-cycled nature of the system, operation in the sub-1 GHz band as well as careful circuit design are employed to reach ultra-low power consumption. The analog front-end was manufactured in 130 nm CMOS and the active circuit area measures 1000 m 1500 m. A maximum channel conversion gain of 50 dB can be achieved. Two symbol rates, 39.0625 Mpulses per second (Mpps) and 19.531 Mpps are supported. The AFE consumes 2.3 mA from a 1.2 V power supply when operating at 39.0625 Mpps. This corresponds to an energy consumption of 70 pJ/pulse. A wireless link over more than 10 m in an office-like environment has been demonstrated at 19.531 Mpps with a PER 1E 3 under direct LOS conditions.

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Section: Full Front-end Measurementscontrasting

confidence: 58%

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

Helleputte

Gielen

2009

IEEE J. Solid-State Circuits

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“…The high-data-rate baseband ADC and digital processor presented in this paper target a custom IR-UWB system [3], [5]. BPSK-modulated Gaussian pulses are transmitted at a pulse repetition frequency (PRF) of 100 MHz in one of fourteen 500-MHz-wide channels within the UWB band [6].…”

Section: High-rate Ir-uwb Architecturesmentioning

confidence: 99%

“…The signal is tracked in the payload using a delay-locked loop (DLL) to account for offsets between the ADC clock frequencies at the transmitter and receiver. Carrier frequency offsets can be estimated and corrected using a Costas loop, as described in [5].…”

Section: B Digital Baseband Processormentioning

confidence: 99%

Low-Power Impulse UWB Architectures and Circuits

Chandrakasan

Lee²,

Wentzloff

et al. 2009

Proc. IEEE

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A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design

et al. 2009

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a b s t r a c tThis works presents an integrated 0:18 mm CMOS 2-PPM demodulator based on a switched capacitor network for an energy detection impulse-radio UWB receiver. The circuit has been designed using a topdown methodology that allows to discover the impact of low-level non-idealities on system-level performance. Through the use of a mixed-signal simulation environment, performance figures have been obtained which helped evaluate the influence at system level of the non-idealities of the most critical block. Results show that the circuit allows the replacement of the ADC typically employed in energy detection receivers and provides about infinite equivalent quantization resolution. The demodulator achieves 190 pJ/bit at 1.8 V.

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A 3.1 to 10.6 GHz 100 Mb/s Pulse-Based Ultra-Wideband Radio Receiver Chipset

Cited by 9 publications

References 12 publications

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers

Low-Power Impulse UWB Architectures and Circuits

A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design

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